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DDR SDRAM PHY FAQ

Denali is proud to present its third-generation Databahn™ Synthesizable DDR SDRAM PHY with the silicon-proven ability to achieve GHz speeds within 4 hours!

3rd gen + 4 hours = 1066 Mhz DDR PHY

Here are answers to some of the most frequently asked questions.

Q: What's new about Denali's synthesizable PHY offerings?

A: Denali's has extended our PHY architecture to include timing closure and DFM, along with 4 hour implementation time. Most customers prefer a synthesizable PHY delivery and this technology allows for flexibility in implementing their particular design.

Q: What is accomplished in 4 hours?

A: With Denali's design and methodology, customers can achieve a GHz PHY (DDR-2133 data rates), including synthesis, layout, and timing closure in four hours using their standard EDA toolset.

Q: How is 1066 MHz (or DDR-2133) achievable?

A: This speed requires a fast foundry process and advanced PHY architecture. Denali's new PHY architecture can achieve this speed. For more details, please contact Denali.

Q: Why would I choose a synthesizable PHY versus a hard PHY?

A: Synthesizing the PHY leaves the customer in full control of their chip. The synthesizable PHY has the architectural flexibility to fit into your floorplan easily. The design is architected in the hierarchical slices for efficient implementation. The PHY supports any arrangement or pitch of the I/O pads and is available in any process node. The PHY looks like other blocks on the chip, so it is easier to integrate with the rest of the chip.

Q: Which process node(s) does the Databahn PHY support?

A: Denali's synthesizable GHz PHY is process-node independent and supports all foundry vendors.

Q: Which memory devices does the Databahn PHY support?

A: Denali's synthesizable GHz PHY supports DDR3/2/1 and LP-DDR1/2 devices.

Q: What additional features make Databahn PHY unique?

A: Denali's GHz PHY is synthesizable and RTL-based, making a perfect fit for your physical chip characteristics and simplifying back-end implementation, carries an extensive silicon-proven track record, and is DFI-compliant, supporting the industry's interface standard. These reasons make Denali's Databahn synthesizable DDR PHY the best solution for deploying memory interfaces in silicon.

Q: Where can I learn more about the PHY features, design details and data slice?

A: For these features and more information, visit www.denali.com/databahn

Q: What are the Databahn PHY deliverables and can I set-up an evaluation?

A: Contact Denali for these details.

Q: Where can I find additional product related information?

A: Databahn DDR-PHY, Databahn DDR Memory Controller IP, DDR-PHY.ORG