Pre-silicon Compliance and Interoperability Solution Accelerates System Design Verification Targeting Computing, Virtualization, and FCoE Products

SUNNYVALE, Calif., February 18, 2010 — Denali Software, Inc., today announced the industry’s first PureSpec-Ethernet verification intellectual property (VIP) product to support the preliminary 40/100 Gigabit(Gb) specification from the IEEE Ethernet Task Force and delivery to current networking and communication customers for use in deploying next-generation Ethernet products. The preliminary specification, which sends Ethernet frames at 40 and 100 gigabits per second, enables developers to take advantage of the increased bandwidth for advanced computing, virtualization, video on demand, Fibre Channel over Ethernet (FCoE), Network-Attached Storage (NAS), VoIP and video surveillance applications. Denali’s PureSpec-Ethernet VIP product provides a comprehensive coverage of the specification and can be integrated into any verification methodology, thus accelerating the pre-silicon design and verification of a variety of Ethernet devices and systems. Denali will be demonstrating its high-quality PureSpec solution for 40/100Gb Ethernet (GbE) design in Booth #1 at the Ethernet Technology Summit in San Jose, California, on February 24-5, 2010.

“Our collection of Ethernet VIP offerings have expanded to include support for 40 Gb/s and 100 Gb/s speeds, providing a further incentive to designers that were waiting on the sidelines for the maturation of the P802.3ba specification and ecosystem,” states Sanjiv Kumar, director, Verification Products at Denali Software. “Our comprehensive verification platform, experience, and support provide the optimal solution for device and system designers aiming to leverage the increased bandwidth features within the new protocol and develop advanced Ethernet marketplace offerings.”

Denali's PureSpec VIP software for the preliminary IEEE P802.3ba specification supports all aspects of the specification including block distribution, lane reordering, alignment insertion, alignment removal, alignment lock per lane, block synchronization per lane, lane deskew, auto-negotiation, as well as the optional sub-layer forward error correction (FEC).

About PureSpec Ethernet Verification IP
Denali’s PureSpec is the most widely used verification IP product for verifying compliance and compatibility of Ethernet designs. All PureSpec products are directly integrated into all popular EDA languages and verification environments including: Verilog, SystemVerilog, VHDL, C/C++, SystemC, 'e', OpenVERA. Quality, completeness and seamless integration with all modern verification environments, e.g., OVM, VMM, eRM, etc., make PureSpec the solution of choice for functional verification and interoperability validation of Ethernet designs. A solid product platform, dedicated customer support, and unmatched EDA modeling and verification expertise make PureSpec Ethernet the best-in-class verification IP solution. Visit: https://www.denali.com/en/products/purespec_gige.jsp for more information about PureSpec-Ethernet.

Longstanding Native Integration of Denali Verification Portfolio with OVM on Mentor’s Questa Verification Platform Provides Verification Engineers Best-in-Class Tools

SUNNYVALE, Calif., Feb. 10, 2010 – Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced a joint Mentor-Denali on-demand webcast about verification maximizing productivity in an Open Verification Methodology (OVM) environment by leveraging Denali PureSpec™ features. The webcast provides a high-level view of several OVM features such as: testbench separation, flexible component instantiation, configurability, sequence stimulus, and TLM communications as well as the implementation of these elements with the industry-standard PureSpec solution for predictable protocol verification.

“The accelerated adoption of OVM has led to increased demands for advanced information to derive the most from OVM,” said Dennis Brophy, director of strategic business development at Mentor Graphics. “Collaborating with Denali has allowed us to put in place an educational webcast that highlights the industry’s most extensive OVM-based portfolio of robust verification solutions along with our best-in-class design and verification environment.”

Denali’s SystemVerilog VIP solutions support an expansive collection of the latest interface and memory technologies, including PCI Express 3.0, SATA, USB 3.0, DDR3, and NAND Flash, enabling seamless integration with OVM and Questa verification platform for accelerated verification closure. Denali’s PureSpec™ and MMAV have supported OVM since the 1.0 specification. Additionally, PureSpec’s transactors, sequence libraries, and scoreboard features can be seamlessly integrated in any OVM-based verification environment to minimize risks improve design quality.

“AppliedMicro values working with leading IP providers, such as Denali, who can provide high-quality products to help us achieve our design requirements in the most cost-effective manner,” said Amal Bommireddy, vice president of engineering at AppliedMicro. “In order to get to market quickly with lower risk of integration errors, AppliedMicro chose Denali verification IP architected for seamless integration into our advanced SystemVerilog design and verification methodology. Denali's products' performance and integration gives us confidence that our end-products will properly interoperate with these industry standard interfaces.”

“We have a large number of customers who use our solutions in an OVM environment to ensure that their designs are fully validated,” said Sanjiv Kumar, director, technical marketing of IP products for Denali. “We are pleased to provide this educational webcast with Mentor to help our mutual customers leverage these features to increase their design and verification productivity.”

About Denali’s Verification IP Portfolio
Denali’s best-in-class, standards-based VIP solutions provides more than 500 companies worldwide the latest technology to design and verify complex chip interfaces for communication, consumer, and computing products. Denali's MMAV and PureSpec products are part of a comprehensive VIP portfolio for predictable compliance of memories and protocol interfaces. Denali’s VIP seamlessly integrates into various testbenches, languages, simulators, and is compliant with popular advanced verification methodologies. For more details, visit: www.denali.com/purespec and www.denali.com/mmav.

Denali's Broad Portfolio of Predictable Protocol Verification IP Products and Protocol Expertise Key Deciding Factors

SUNNYVALE, Calif., Feb. 4, 2010 — Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Marvell, a world leader in the development of storage, communications, and consumer silicon solutions, has signed an expanded business agreement that establishes Denali as an IP partner thus enabling a company-wide adoption of Denali's comprehensive line of verification IP (VIP) products to speed the design and verification of Marvell's future products for various applications. Marvell is using Denali’s PureSuite™ compliance suite, PureSpec™ and MMAV™ for functional verification of complex interface protocols such as: PCIe 3/2/1, USB 3/2, Ethernet, and SATA 3/2. By utilizing Denali’s products, Marvell’s design and verification teams can improve their time-to-market with lower risk of integration errors, integrate the IP seamlessly into their design and verification methodology and deliver the confidence that their end-products are designed to properly interoperate with these industry standard interfaces.

“Our leadership in technology innovation and successful delivery of highly complex SoCs and our track record of first-silicon successes are complemented by Denali and their ability to meet a variety of our product requirements,” said Dr. Pantas Sutardja, vice president and Chief Technology Officer and Chief Research and Development Officer at Marvell. “Denali has provided impressive design tool quality, performance and protocol expertise. They have demonstrated their protocol expertise with the latest specifications and we look forward to our continued collaboration with Denali as we develop our next-generation applications.”

“Denali understands the important technical challenges facing Marvell's design methodology for chip and system development. Our verification IP products, which include support for the latest PCIe, USB, SATA and Ethernet specifications help to ensure that Marvell will be able to meet aggressive schedules for their designs,” said David Lin, vice president of Marketing at Denali Software. "Our industry leading products will help Marvell's SoC designers accelerate their design time, meet their performance goals and help them achieve a competitive advantage.”

About Denali VIP Solutions
Denali’s best-in-class, standards-based verification IP (VIP) solutions provides more than 500 companies worldwide the latest technology to design and verify complex chip interfaces for communication, consumer, and computing products. Denali's MMAV™ and PureSpec™ products are part of a comprehensive VIP portfolio for predictable compliance of memories and protocol interfaces. Denali’s VIP seamlessly integrates into various testbenches, languages, simulators, and is compliant with popular advanced verification methodologies (e.g., OVM, VMM, eRM, etc.). For more info about these products, visit www.denali.com/purespec.

Advanced Phase PHY Incorporates An Innovative Over-Sampling Approach Achieving Rapid Implementation Times for High-Performance Memory Systems

SUNNYVALE, Calif., December 10, 2009 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today revealed a new phase PHY technology for DDR SDRAM physical interfaces, delivering memory system performance up to 1066 MHz clock speeds (or DDR-2133 data rates) on 65-nanometer foundry process nodes or lower. Denali’s phase PHY technology applies a high-speed oversampling architecture paired with per-bit data capture and calibration mechanism to achieve GHz clock rates. This third-generation DDR PHY technology is delivered as a fully-synchronous design which benefits design teams with the configurability needed to satisfy their physical implementation requirements.

As DDR SDRAM devices reach 2133 Mbps data rates, bit-to-bit skews within the data lanes become significant fractions of the data window. Denali’s oversampling architecture employs an 8- or 16-phase lock loop (PLL) and performs pattern matching to determine the correct data sample points for DDR data for each transaction. By managing the data capture on a per-bit basis (rather than on a per-byte basis), Denali’s PHY reliably closes timing at 1066 MHz clock rates. Furthermore, differences in the routing of data and data strobe signals are calibrated in the silicon eliminating the need for time-consuming hand layout. The fully-synchronous design provides flexibility for floorplanning, pin placement, and power routing and uses standard EDA toolsets to easily realize a reliable implementation.

“The continued demand for increased bandwidth in various internet and electronic applications is driving the need for DDR3 technology and for the ability to support data rates up to 2133 Mbp/s,” states Mike McKeon, director of PHY IP at Denali. “Our DDR phase PHY is cutting-edge technology, delivering effective management of GHz clock speeds and a perfect match for our customers’ specific design implementation needs.”

About Databahn DDR PHY Solutions
Denali’s Databahn DDR PHY is a complete solution ready to be integrated into SoCs and ASICs which interface with DDR memories. Each PHY is delivered to match the unique requirements of the customer’s DDR application. The PHY is configurable for data width, ECC, low power, and many other options, and supports DDR3/2 and LP-DDR1/2 devices. For more info, visit: www.denali.com/ddrphy, Databahn PHY Frequently Asked Questions, and Animated Guide to Denali DDR PHY.

High-Quality Verification IP Portfolio Accelerates Design and Verification
Of High-Performance Processors

SUNNYVALE, Calif., Dec. 8, 2009 — Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Ubicom, a leading provider of networking and multimedia processor solutions, has extended its relationship with Denali, taking full advantage of its advanced protocol verification technology and services. Ubicom has selected Denali’s MMAV™ and PureSpec™ verification IP (VIP), which support high-speed communications and peripheral protocols, to aid in the design and verification of their media and network processors. Denali’s MMAV and PureSpec fortifies Ubicom’s designers with a predictable protocol verification IP solution to meet their design requirements and lower integration risk, ensuring interoperability with new products.

“Our hardware and software innovations enable multimedia and networking products that ensure a high-quality user experience and unprecedented ease of use,” states Jon Gibbons, vice president of VLSI Engineering at Ubicom. “Denali has consistently provided robust, high-quality verification IP solutions and reaffirmed their superb industry reputation for protocol expertise. We are confident that their solutions will continue to enable our designers to take advantage of the latest protocol features and quickly create innovative products with less risk and improved time-to market.”

As a leading provider of networking and multimedia processor solutions, Ubicom delivers communications and media processor and software platforms that address the unique demands of real-time interactive applications and multimedia content delivery in the digital home. Ubicom will utilize Denali’s PureSpec and MMAV products in their in their next generation of multimedia and network processors.

“SoC design and verification teams look to Denali to provide the industry’s best-in-class verification solutions to accelerate the pre-silicon design and verification of protocol applications,” states Sanjiv Kumar, director, Verification Products at Denali Software. “We value Ubicom’s trust in Denali and are confident that our predictable protocol verification IP will minimize risks and increase design productivity.”

About Denali’s Verification IP Portfolio
Denali’s best-in-class, standards-based verification IP (VIP) solutions provides more than 500 companies worldwide the latest technology to design and verify complex chip interfaces for communication, consumer, and computing products. Denali's MMAV and PureSpec products are part of a comprehensive VIP portfolio for predictable compliance of memories and protocol interfaces. Denali’s VIP seamlessly integrates into various testbenches, languages, simulators, and is compliant with popular advanced verification methodologies (e.g., OVM, VMM, eRM, etc.). For more details, visit: www.denali.com/purespec and www.denali.com/mmav.

Best-in-Class Solutions Speed Design-to-Silicon Success of PCI Express Technology

SUNNYVALE, Calif., Oct. 20, 2009 — Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Cray has adopted Denali Databahn™ PCI Express (PCIe) controller core and PureSpec™ verification IP (VIP), which support the latest PCIe 3.0 specifications from the PCI-SIG. The 16-lane PCIe 3.0 controller from Denali can deliver 128 GT/s of raw bandwidth, surpassing a 100G Ethernet interface. This is equivalent to transferring a full 3-hour high-definition movie file in under one second.

“Our systems are deployed in mission critical applications and require superior performance, scalability, and reliability. After examining the available solutions in the industry, it was clear that Denali was more than capable of delivering a PCI Express 3.0 controller with the critical features that we needed,” states Peg Williams, senior vice president of research and development at Cray. “Not only has Denali met our functional and performance requirements, but their reputable technology, verification expertise and strong customer reputation made them a valued supplier.”

As a global leader in supercomputing, Cray provides supercomputing, storage and data management technologies to government, industry and academia. Cray technology enables scientists and engineers to achieve remarkable breakthroughs by accelerating performance, improving efficiency and extending the capabilities of their most demanding applications. Last year, the Cray XT5 system, nicknamed “Jaguar” and located at the Oak Ridge National Laboratory, was number two on the list of the World's Top 500 Supercomputers.

“Denali continues to provide the industry’s highest-quality IP solutions for PCIe technology, which enables our customers, such as Cray, to reduce their design risk and enable them to develop complex projects on schedule,” remarks Ashwin Matta, Director of PCIe Core Technology for Denali Software. “We value Cray's trust in Denali and are confident that our design and verification IP products will accelerate their design time, meet their performance goals and help them achieve a competitive advantage.”

About Databahn PCI Express Solutions
Denali's Databahn PCIe cores and PureSpec verification IP software for PCI Express provide full support of the latest capabilities, such as: Internal Error Reporting, ID Based Ordering, TLP Processing Hints, Optimized Buffer Flush/Fill, Atomic Operations, Re-Sizable BAR, Extended TAG Enable, Dynamic Power Allocation, and Latency Tolerance Reporting. For more info about Databahn and PureSpec, visit www.denali.com/pcie.

High-Quality, Configurable DDR PHY Deployed in Video Processing Chips For AV Receivers and Blu-ray Players

SUNNYVALE, Calif., October 15, 2009 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Anchor Bay, a leading supplier of video-processing semiconductors (ASICs) and systems, has successfully taped out its ABT2015 chip utilizing Denali’s next-generation Databahn™ DDR PHY solution in 65-nanometer(nm) Common Platform™ process technology offered by IBM, Chartered Semiconductor Manufacturing Ltd., and Samsung Electronics Co., Ltd. Denali’s Databahn solution enabled Anchor Bay’s developers to meet optimal performance design requirements in their high-volume SoCs for video processing semiconductor products that advancing the optimum home theater experience.

“The superior quality produced by our advanced video processing algorithms places high demands on the performance of the DDR interface,” said Satish Iyengar, Director, Semiconductor Engineering at Anchor Bay. “Denali’s Databahn DDR synthesizable PHY was configurable, high-quality and delivered what no other vendor could within our time-to-market constraints. Denali’s demonstrated the industry’s best expertise and customer support and their PHY solution helped address our performance and design requirements.”

Anchor Bay’s ABT2015 chip is ideally suited for video processing functions in A/V receivers, Blu-ray player recorders, and digital displays. The chip includes all of Anchor Bay’s award winning Video Reference Series™ technologies, including PReP™ (Progressive ReProcessing), Precision Deinterlacing™ , Precision Video Scaling™, Mosquito Noise Reduction and Picture Enhancement. The ABT2015 supports HDMI 1.3 Deep Color and is pin-out compatible with the ABT2010.

Anchor Bay used Denali’s DFI-compliant PHY with their own in-house memory controller, reducing the integration effort by using this industry standardized interface. Denali’s Databahn DDR PHY product offers a powerful, feature-rich technology for creating and implementing DDR PHY without the need for custom layout services. The DDR-PHY provides a configurable platform for specifying the unique functional and physical PHY characteristics for a given customer application. This specification results in a custom synthesizable design and scripts for constraints and timing validation suitable for automated place and route implementation tools.

“Consumer SoCs require specialized DDR memory systems that must address performance, quality, and time-to-market,” said Mike McKeon, director, PHY Technology for Denali. “The Databahn DDR PHY solution provides optimal configurability and quality while enabling flexible power management schemes for a variety of next-generation digital television and high-definition digital video applications. We are pleased to have been able to work with Anchor Bay and help them meet their aggressive time-to-market schedule.”

About Databahn DDR PHY Solutions
Denali’s Databahn DDR PHY is a complete solution ready to be integrated into SoCs and ASICs which interface with DDR memories. Each PHY is delivered to match the unique requirements of the customer’s DDR application. The PHY is configurable for data width, ECC, low power, and many other options, and supports DDR1/2/3 and LP-DDR1/2 devices. For more info, visit: www.denali.com/dram.

Predictable Protocol Verification IP Solution Speeds Development of Power Architecture-Based Designs

SUNNYVALE, Calif., Sept. 16, 2009 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced Denali’s PureSpec™ verification IP support for IBM’s PowerPC® processor local bus (PLB)-6, enabling verification of compliance with the latest PLB specification and validation of interoperability between the processor cores and integrated bus controllers. The high-quality, platform independent toolkits incorporates a set of IBM qualified solutions that provides a complete environment aimed to streamline Power Architecture™-based and IBM CoreConnect™ designs.

“We work to insure our customers have access to best-in-class products in our ecosystem, such as Denali’s PureSpec, a high-quality comprehensive verification IP solution,” said Jim Cuffney, Executive Project Manager, PowerPC Cores Development at IBM Microelectronics. “IBM’s collaboration with Denali gives designers the ability to quickly implement customized Power Architecture based applications in world-leading semiconductor technologies.”

Denali suits its comprehensive PureSpec verification IP product with test-plan generation based on the protocol specifics and design parameters, seamless integration to verification methodologies (VMM, OVM, and eRM) and third-party planners enabling automated verification and back-annotation of the coverage data to the test plan.

“Our long-standing relationship with IBM, membership in Power.org, and delivery of comprehensive verification IP solutions continues to be a touchstone for enabling customer success,” remarks David Lin, vice president of Marketing at Denali Software. “Our predictable protocol verification IP product for PLB-6 helps customers minimize risk and increase higher-quality IBM’s CoreConnect™ on-chip bus and Power Architecture-based SoCs.”

About Denali PureSpec
PureSpec is a predictable verification solution for protocol compliance and enables verification planning and coverage-driven verification closure. PureSpec verification solution includes a configurable bus functional model, protocol monitor, and complete assertion library for all components in the topology. PureSpec additionally provides an integrated data generation engine to help drive defined, pseudo-random bus traffic at all layers. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design. For more product information, visit: www.denali.com/purespec.

Denali’s Databahn Flash Controller IP and PHY IP Delivers Performance Using ONFi2 NAND Devices for ASIC and FPGA Designs

SUNNYVALE, Calif., Aug. 10, 2009 — Denali, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Micron Technology, Inc., has validated Denali’s Databahn™ NAND Flash controller IP and FlashPoint™ products with its line of ONFI 2-based flash devices. Denali’s products provide designers with a complete solution to maximize the performance capabilities of the new high-speed ONFi 2 devices from Micron, using either single-level cell (SLC) or multi-level cell (MLC) technology. Denali’s Databahn NAND controllers and FlashPoint platform for ONFi 2 are configurable and programmable for optimal performance in a range of applications, from solid state drives (SSDs) and cache for consumer computing to enterprise server systems.

"The ONFi source-synchronous interface can be found in all of Micron’s 34nm MLC and SLC NAND products, providing customers with a fast read and write throughput that breaks through the interface bottlenecks of traditional NAND, which is especially important for today’s NAND-based computing applications, such as SSDs,” said Kevin Kilbuck, Director of Strategic NAND marketing at Micron. "We believe Denali’s NAND flash controller technology will provide a high-quality, hardware accelerated architecture to our customers, which leverages the features and functionality of our ONFi 2.1 devices.”

Denali’s Databahn NAND Flash controller utilizes advanced ECC algorithms, hardware code correction and multiple page size, plus supports legacy asynchronous flash devices and all ONFi modes. Coupled with a configurable PHY, the controller IP provides systems developers with a high-performance and interoperable product for deploying NAND Flash in next-generation system designs. For more info about Denali’s NAND Flash solutions, visit: www.denali.com/flash.

The FlashPoint platform is a complete system design with interface solutions to NAND Flash memory. The platform uses a unique design configuration engine that enables the system to be tuned for optimal performance with differentiating features for a range of products, including PC cache modules, SSDs, and ExpressCard™ devices.

“ONFi 2.0 is becoming a key requirement for many types of high-performance NAND Flash applications,” said Robert Pierce, senior director of Flash Products at Denali Software. “We are pleased to be working with Micron to provide our mutual customers enabling technologies, such as our NAND Flash controller IP and PHY, to quickly deploy ONFi 2 technology in their product designs, thus minimizing time-consuming hardware and software development and maximizing the benefits of its performance features.”

Protocol Expertise Provides Foundation for Verification Planning and Exploration

SUNNYVALE, Calif., July 23, 2009 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced the availability of the extended PureSpec™ verification IP solution with planning and protocol exploration capabilities, plus seamless integration into 3rd party verification planners, such as Synopsys® VMM Planner. These predictable protocol verification features enable design and verification engineers to accelerate and achieve verification closure. Visit the Denali booth (#1424) at DAC for a live VMM Planner demonstration.

“The new release of Denali’s PureSpec addresses the expertise and predictability gap in the verification of complex protocols,” states Dr. Ambar Sarkar, Chief Verification Technologist at Paradigm Works. “They have been leading the industry with their comprehensive verification IP solutions for protocols, like PCI Express and USB, and these breakthrough capabilities will certainly increase adoption.”

Denali’s PureSpec verification solution generates a customized and comprehensive hierarchical test plan based on protocol specifics and design parameters. This planning feature provides design and verification engineers with an unbiased and complete test plan in standard formats, offering a transparent and objective measurement scale.

The protocol explorer within PureSpec provides visibility into protocol concepts and objects, instead of simple wave forms. This context sensitive and protocol-aware debugger facilitates the reporting of state machines and properties, and back tracing of data packets and protocol events, thus shortening the debugging cycle times.

Additionally, PureSpec enables seamless integration with advanced verification methodologies and third party planners enabling automated verification and back-annotation of the coverage data to the test plan. This tight integration closes the loop and substantially improves the predictability of the verification process. Denali’s CTO, Mark Gogolewski, will present at the Synopsys Interoperability Breakfast on Wednesday, July 29, “Peace, Love and Interoperability: Improving Quality & Productivity with Verification & Custom Design Standards” which will highlight PureSpec’s integration with VMM Planner.

“Language and methodology standards have a major impact on customers’ verification interoperability and productivity,” said Yatin Trivedi, director of standards at Synopsys. “Denali’s support for the VMM methodology, including their new verification plans compatible with Synopsys’ VMM Planner, benefits the growing VMM ecosystem.”

“Protocol expertise plays an important role when addressing today’s complex verification challenges,” states Sanjiv Kumar, director, Verification IP products at Denali. “Our PureSpec product enables automated validation of a protocol interface through high-quality test plans, sequence and assertion libraries and BFM via any coverage driven methodology. Denali PureSpec further delivers a powerful capability for protocol-aware exploration and intuitive debugging.”

About Denali PureSpec
PureSpec is a predictable verification solution for protocol compliance and enables verification planning and coverage-driven verification closure. PureSpec verification solution includes a configurable bus functional model, protocol monitor, and complete assertion library for all components in the topology. PureSpec additionally provides an integrated data generation engine to help drive defined, pseudo-random bus traffic at all layers. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design. For more product information, visit: www.denali.com/purespec.