High-Quality Databahn DDR3/2 SDRAM Controller and DFI-Compliant Synthesizable GHz PHY Utilized in Various eMPUs for Communication, Display and Networked Devices

SUNNYVALE, Calif., June 9, 2010 – Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that STMicroelectronics, a global leader in developing and delivering SoC and semiconductor solutions, has integrated Denali’s configurable Databahn® DDR3/DDR2 SDRAM multiport memory controller IP and DFI-compliant Synthesizable GHz PHY IP as a baseline solution for the Structured Processor Enhanced Architecture (SPEAr®) embedded microprocessor platform. STMicroelectronics’ engineers were able to meet their specific design requirements and add configurability to their chips by leveraging the Databahn controller and PHY IP for their SPEAr family of microprocessors (SPEAr600 and later). The new SPEAr1300 product line architecture provides substantial breakthrough in computing power and connectivity for networked devices and will be used for communication, display and control applications.

“We selected Denali because of its established leadership in delivering high-quality IP and PHY technology, which has been silicon-proven in a wide range of our high-performance SoC designs,” remarks Stefano Ravaglia, SoC R&D director at STMicroelectronics. “Our new-generation SPEAr family of embedded microprocessor technologies targets many of today’s computing and connectivity requirements. Denali’s Databahn controller IP and PHY can be easily implemented in our advanced HCMOS process technologies providing the marketplace with the optimal solutions to streamline embedded SoC designs.”

STMicroelectronics’ SPEAr family of microprocessors targets embedded-control applications across market segments from computer peripherals and communications to industrial automation. These devices allow equipment manufacturers to develop complex yet flexible digital engines with remarkable time and cost savings during the design cycle. STMicroelectronics’s SPEAr multi-application chips are manufactured in state-of-the-art, low-power 90, 65, and 55nm HCMOS (high-speed CMOS) process technologies and provide high levels of computing power and connectivity.

“As the leading provider in connectivity IP, we continue to provide customers such as STMicroelectronics with comprehensive, high-quality solutions that reduce design risk and enable them to develop complex chips on schedule,” commented Marc Greenberg, director, Technical Marketing at Denali Software. “We appreciate ST’s trust in Denali and welcome the opportunity to help them ramp their SoC designs to volume production faster.”

About Databahn DDR SDRAM Solutions
Denali’s Databahn configurable, high-performance memory controller ensures compatibility with all the latest high-speed SDRAM technologies, including the many DDR3/2 and LPDDR2/1 devices offered by all major memory vendors. The Databahn controller IP has been proven in all major commercial process technology nodes. Databahn controllers are DFI-compliant (DFI is the industry’s standard interface between memory controllers and PHYs), they are highly configurable, and they are easy-to-integrate into a chip design, making them an appropriate match for a wide range of system architectures. For more info, visit: www.denali.com/dram.

Collaboration with Denali Software Achieves High-Quality Databahn LPDDR2 SDRAM Controller IP and DFI-Compliant PHY Enables 400 MHz On Advanced 45-nm Process Technology

SUNNYVALE, Calif., May 19, 2010 – Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that ST-Ericsson, a global leader in wireless semiconductors and mobile platforms, has leveraged Denali’s high-performance Databahn Low-Power Double Data Rate 2 (LPDDR2) Synchronous DRAM (SDRAM) controller IP along with STMicroelectronics’ DFI-compliant Physical IP (PHY) in its smartphone platform the U8500 on STMicroelectronics’ advanced low-power 45-nanometer (nm) CMOS manufacturing technology. The U8500 smartphone platform achieved data rates up to 800 Megabits per second per pin at 400 MHz on LPDDR2 interfaces and is an ideal solution for engineers targeting low-power mobile applications. By utilizing Denali’s design IP, ST-Ericsson was able to accelerate its LPDDR2 memory system design, lower its integration risk, and speed its time-to-market for its new innovative cell-phone chip.

According to STMicroelectronics, Denali’s configurable controller IP provides the highest level of quality required from a technology vendor. STMicroelectronics’ state-of the-art 1.2V LPDDR2 Input/Output pads (I/O) sustain 800Mbps at 8.5pF across full PVT range ensuring precision output impedance, with programmable drive to adapt various load conditions on board, compliant with all Electrostatic Discharge (ESD) standard levels.

Denali’s Databahn LPDDR2 controller IP features automatic power control for self-refresh, power-down, and dynamic frequency scaling (DFS). Additionally, the LPDDR2 controller enables the implementation of power domain retention, source-biasing, and shut-off to meet the stringent power requirements required for mobile applications.

“This recent success demonstrates our commitment to provide our customers with advanced solutions that speed time-to-market on leading-edge process technologies,” commented Mark Gogolewski, CTO of Denali Software. “Our low-power IP solutions and ST-Ericsson’s power-reduction technologies help designers targeting mobile applications to rapidly move from tape-out to production silicon with lower system development costs, and improve performance and reliability.”

About Databahn DDR SDRAM Solutions
Denali’s Databahn DDR memory high-performance solution ensures compatibility with all the latest high-speed memory technologies, including the many DDR3/2 and LPDDR2/1 devices from all major memory vendors, and supports all process technology nodes. Databahn DRAM memory controllers are DFI-compliant, highly configurable, and easy-to-integrate, enabling an opportune match for a wide range of system architectures. For more info, visit: www.denali.com/dram and www.ddr-phy.org.

About Denali Software
Denali Software, Inc., is a leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying PCI Express, USB, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.
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Denali and Denali Software are registered trademarks of Denali Software, Inc. Databahn is a trademark of Denali Software, Inc. All other trademarks are of their respective owners.

Complementary Transaction Supports Cadence’s EDA360 Vision

SAN JOSE and SUNNYVALE, Calif. – May 13, 2010 – Cadence Design Systems, Inc. (Nasdaq: CDNS), a leader in global electronic design innovation, and Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that the companies have entered into a definitive merger agreement under which Cadence will acquire Denali for $315 million in cash. Denali is expected to have approximately $45 million in cash at closing. In alignment with its EDA360 strategy, this transaction expands Cadence’s solution portfolio to deliver efficient and cost-effective system component modeling and IP integration. The transaction was unanimously approved by the Cadence and Denali Boards of Directors.

"Denali’s strengths in Memory Models, Design IP, and Verification IP accelerate the execution of Cadence's recently announced EDA360 vision, creating new opportunities for the company," said Lip-Bu Tan, president and chief executive officer of Cadence. "We are excited to welcome Denali's talented employees and look forward to delivering the value inherent in this combination."

"Bringing our two companies together provides a path for future growth, as well as expanded opportunities for our customers and employees," said Sanjay Srivastava, president and chief executive officer of Denali. "Cadence is a leader in global electronic design and is the right match for Denali and its employees. I am personally excited to be a part of the Cadence team and to help realize the EDA360 vision."

EDA360 centers on three components: (1) System Realization - the development of a complete hardware/software platform with all of the capabilities needed to begin applications development and deployment; (2) SoC Realization - the development of a single system on chip (SoC), including silicon IP and "bare-metal" software; and (3) Silicon Realization - everything required to get a design into silicon, including the creation and integration of large digital, analog, and mixed-signal IP blocks.

The merger will accelerate the delivery of the solutions outlined in this vision:

• Denali's memory models provide system component modeling and verification capabilities required in System Realization.
• Denali's Design IP products enhance the Cadence Open Integration Platform required in SoC Realization.
• Denali's ease-of-use and well-established support of third-party simulators by its Verification IP (VIP), coupled with the focus on metric-driven and compliance management of Cadence's VIP, make this combination highly complementary and necessary for SoC Realization, and enable Cadence to expand its third-party simulation support.

Cadence intends to finance the transaction with available cash. The transaction is expected to be accretive to Cadence’s fiscal year 2011 earnings per share.

For more information, see the Question and Answer document on the Cadence website at www.cadence.com/cadence/investor_relations/Documents/DenaliQA.pdf.

Audio Webcast Scheduled
Lip-Bu Tan, Cadence's president and chief executive officer, and Kevin S. Palatnik, Cadence's senior vice president and chief financial officer, will host an audio webcast to discuss the merger on May 13, 2010, at 5:30 a.m. (Pacific) / 8:30 a.m. (Eastern). Attendees are asked to register at the Web site at least 10 minutes prior to the scheduled webcast. An archive of the webcast will be available starting May 13, 2010 at 8:30 a.m. (Pacific) and ending May 20, 2010 at 8:30 a.m. (Pacific). Webcast access is available at www.cadence.com/company/investor_relations.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design, verify, and implement advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, California, with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

About Denali
Denali is a world-leading provider of electronic design automation (EDA) tools, intellectual property (IP), software and design platforms for system-on-chip (SoC) design and verification. Denali delivers the industry's most widely-used solutions for deploying PCI Express, USB, NAND Flash and DDR SDRAM subsystems in electronic designs. Developers use Denali's EDA, IP products, and services to simplify design, reduce risk, and accelerate time-to-market for their complex SoC designs. Founded in 1995, Denali is headquartered in Sunnyvale, California and serves the global electronics industry with direct sales and support offices in North America, Europe, Japan, and Asia. www.denali.com.

The statements contained above regarding when Cadence expects to complete the transaction and when it expects the transaction to be accretive, as well as the statements by Lip-Bu Tan, Cadence president and chief executive officer, Kevin S. Palatnik, Cadence senior vice president and chief financial officer, and Sanjay Srivastava, Denali president and chief executive officer, include forward-looking statements based on current expectations or beliefs, as well as a number of preliminary assumptions about future events that are subject to factors and uncertainties that could cause actual results to differ materially from those described in the forward-looking statements. Readers are cautioned not to put undue reliance on these forward-looking statements, which are not a guarantee of future performance and are subject to a number of risks, uncertainties and other factors, many of which are outside Cadence's control, including, among others: (i) failure or inability to consummate the merger, effects of the merger on Cadence's financial results, the effect of regulatory approvals, the difficulty in determining the fair value of Denali, the results of an audit of Denali's financial statements, the potential inability to successfully operate or integrate Denali's business, including the potential inability to retain customers, key employees or vendors; (ii) the effect of the announcement of the merger on Cadence's and Denali's respective businesses, including the possibility that the announcement may result in delays in customers purchases of products or services; (iii) Cadence's ability to compete successfully in the electronic design automation product and the commercial electronic design and methodology services industries; (iv) Cadence's ability to successfully complete and realize the expected benefits of the previously disclosed restructurings without significant unexpected costs or delays, and the success of Cadence's other efforts to improve operational efficiency and growth; (v) the mix of products and services sold and the timing of significant orders for Cadence's products, and its shift to a ratable license structure, which may result in changes in the mix of license types; (vi) change in customer demands, including the possibility that the previously disclosed restructurings and other efforts to improve operational efficiency could result in delays in customers' purchases of products and services; (vii) economic and industry conditions in regions in which Cadence and Denali do business; (viii) fluctuations in rates of exchange between the U.S. dollar and the currencies of other countries in which Cadence does business; (ix) capital expenditure requirements, legislative or regulatory requirements, interest rates and Cadence's ability to access capital and debt markets; (x) the effects of the previously disclosed restructurings and other efforts to improve operational efficiency on Cadence's business, including its strategic and customer relationships, ability to retain key employees and stock prices; (xi) events that affect the reserves Cadence may take from time to time with respect to accounts receivable, taxes, litigation or other matters; and (xii) the effects of any litigation or other proceedings to which Cadence is or may become a party.
For a detailed discussion of these and other cautionary statements related to our business, please refer to Cadence's filings with the Securities and Exchange Commission. These include Cadence's Annual Report on Form 10-K for the year ended January 2, 2010, Cadence's Quarterly Report on Form 10-Q for the quarter ended April 3, 2010 and Cadence’s future filings.

Cadence Contacts:

Investors and Shareholders
Jennifer Jordan
408-944-7100

Media
Lynne Cox
408-944-7669

Databahn Configurable DDR2/3 Controller Delivers Best Solution for
High-End Video Applications

SUNNYVALE, Calif., April 27, 2010 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Pixelworks (NASDAQ: PXLW), an innovative provider of powerful video and pixel processing technology, has selected Denali’s Databahn™ DFI-compliant DDR3/2 memory controller IP for its upcoming IC designs targeting innovative products for the advanced video display market. Databahn enables Pixelworks’ developers to meet performance goals in their high-volume SoCs for professional and consumer product designs.

“Denali’s DDR controller IP solution allows Pixelworks to meet the design requirements of our OEM customers,” said John Lau, vice president, China General Manager of Pixelworks. “Denali’s DDR memory controller is unmatched in performance and represents the highest quality IP solution in the industry. Denali’s expertise and reputation were key factors in our decision to use their solution to aid us in addressing higher speed timing closure issues.”

The Databahn product provides a comprehensive infrastructure for configuring, analyzing, and generating the optimal memory controller for a given customer application. Denali’s Databahn DDR-SDRAM memory controllers offer a powerful, multi-port solution with configurable features and functionality to satisfy system performance requirements in terms of bandwidth, latency, and power. In addition, the Databahn memory controller reduces the required effort needed to integrate with DDR PHYs by supporting the latest version of the industry-standard DDR PHY Interface (DFI) specification.

“Consumer SoCs require specialized DDR memory systems that can address performance, quality, and time-to-market,” said Marc Greenberg, director, Technical Marketing of IP products for Denali. “The Databahn DDR controller solution provides optimal performance while enabling flexible power management schemes for a variety of video, broadband, and network displayed applications. We are pleased to be working with Pixelworks and look forward to helping them meet their aggressive time-to-market schedules as they develop and deliver their innovative new processors for high-end digital video applications.”

About Databahn DDR Memory Solutions
Denali’s Databahn DDR-SDRAM memory solutions ensure compatibility with all the latest high-speed memory technologies, including the many DDR2, DDR3, and LP-DDR2 devices from all major memory vendors, and supports all vendor process nodes. Databahn controllers are DFI compliant and highly configurable, enabling an opportune match for a wide range of system architectures. For more info, visit: www.denali.com/dram.

LPDDR1-SDRAM Controller and PHY Solution Enables 30 Percent Power Savings For Pocket TVs and Portable Media Players

SUNNYVALE, Calif., April 14, 2010 — Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Augusta Technology USA, a mobile digital solutions company, has selected Denali’s Databahn™ LPDDR1-SDRAM controller and PHY intellectual property (IP) products for incorporation into its latest processor, designed using TSMC’s Low Power (LP) process technology. The low-power processor solution enables mobile manufacturers to cost-effectively incorporate digital broadcast TV reception and other popular multimedia features into various portable devices such as cellular phones, portable media players, pocket TVs, smartphone PDAs, and vehicle media centers. Augusta’s engineers are using the unique power-saving features available in Denali’s LPDDR controller and PHY to achieve optimal system-level performance for the DRAM subsystem in Augusta’s processor design.

“As a provider of leading-edge mobile digital solutions, we are always looking to take advantage of the latest advances in low-power technologies,” said Aki Shohara, CTO at Augusta Technology USA. “Our engineers who have extensive and successful silicon design experience for mobile solutions, particularly with respect to power-saving optimization, selected Denali’s Databahn controller and PHY for our next mobile chip after careful evaluation. Denali’s high-quality LPDDR controller, PHY solutions and domain expertise were key factors in the selection to achieve our design requirements and to meet our time to market goals.”

The low-power features of Denali’s Databahn DRAM controller and memory PHY allow mobile systems to manage memory power usage either automatically or manually, whichever best suits the overall system design and power/performance goals. Databahn’s high-performance algorithms improve memory utilization. When combined with low-power IC process technology, systems can extract high-bandwidth performance from DRAM subsystems while operating them at low power. The PHY incorporates a digital delay locked loop (DLL) that reduces power consumption while still achieving high-performance design goals. In addition, IC designers find the PHY’s DLL easy to implement in silicon. The PHY’s low-power architecture combined with the memory controller’s intelligent management of the low-power modes built into commercial DDR memory cuts memory-subsystem power consumption by 30%. These advanced DRAM-management technologies and more will be highlighted at the upcoming MemCon event, “Roadmap: GHZ DDR3 and Beyond,” on July 28th, in Santa Clara, CA.

“Next-generation mobile SoCs that incorporate specialized DDR memory systems must deliver low-power features with very high-quality and within tight market windows,” states Marc Greenberg, director, technical marketing of IP products for Denali Software. “Our Databahn controller and PHY IP products not only provide optimal configurability and quality, but also incorporate flexible power-management options for a variety of next-generation portable digital television applications. We are pleased to have been able to work with Augusta Technology and help them meet their aggressive time-to-market schedules.”

About Databahn DDR Memory Solutions
Together, Denali's Databahn DDR controller and PHY constitute a complete solution that’s ready to be integrated into SoCs and ASICs. They ensure compatibility with all the latest high-speed, low-power memory technologies. This combination supports all memory component specifications, including all the latest DDR3/2/1 and LPDDR2/1 devices from all major memory vendors and support for all vendor process nodes. The PHY is configurable for data width, ECC, low power, and other options, and is delivered to match the unique requirements of a specific DDR application. For more info, visit: www.denali.com/databahn.

Collaboration Springs High-Quality DDR-SDRAM C-Based Models for Enhanced System-Level Simulation and Performance Analysis

SUNNYVALE, Calif., Mar. 24, 2010 – Denali Software, Inc., a leading provider of intellectual property (IP) and electronic design automation (EDA) software, and Carbon Design Systems today announced a collaboration to provide designers with cycle-accurate models of Denali’s configurable Databahn™ DDR SDRAM controller IP for virtual platforms. Databahn IP models are available today for use with leading system simulation environments (including Carbon SoC Designer, CoWare Platform Architect, and OSCI SystemC) to perform architectural analysis, validate system performance, and perform hardware/software integration prior to silicon.

“We are extremely pleased to have Denali join our growing IP community,” stated Bill Neifert, vice president of Business Development at Carbon. “Our customers are using Denali’s high-performance Databahn DDR-SDRAM IP to architect some of the world’s most complex system on chip (SoC) designs. Adding Databahn DDR memory interface models to our IP offerings gives our mutual customers the ability to leverage the advanced capabilities of the platform across more of their designs.”

DDR SDRAM plays a critical role in overall system performance in a variety of applications including consumer, communications, and computing. This collaboration delivers 100% cycle-accurate models of this vital IP to the engineers who need it most: architects making critical performance tradeoffs and firmware developers debugging presilicon software. Cycle-accurate models are available immediately from Carbon Design Systems for all SDRAM memory interface IP in the Databahn portfolio, including support for the latest DDR3, DDR2, and LPDDR2 specifications.

“Denali is committed to expanding the ecosystem around our broad range of high-quality controller IP to ease our customers’ design process,” said Marc Greenberg, director, Technical Marketing at Denali Software. “Partnering with Carbon to make models of our DDR SDRAM controller cores available in SoC Designer and other virtual environments gives our customers access to a valuable platform to perform architectural exploration, optimize system performance, and debug complex firmware issues earlier and more accurately than previously possible.”

About Databahn DDR and PHY Solution
Denali’s Databahn DDR-SDRAM controller and synthesizable PHY IP is a complete solution ready to be integrated into SoCs and ASICs which interface with DDR memories. Each controller and PHY is delivered to match the unique requirements of the customer’s DDR application. These are configurable for data width, ECC, low power, and many other options, and supports DDR1/2/3 and LP-DDR1/2 devices. For more information about Databahn DDR-SDRAM and PHY solution, visit: http://www.denali.com/dram.

Industry Executive Discusses Achieving High-Quality Design and Verification at Low Expense Amidst Today’s Skyrocketing Costs

SUNNYVALE, Calif., Mar. 18, 2010 – Denali Software, Inc., a leading provider of intellectual property (IP) and electronic design automation (EDA) software, today announced that Mark Gogolewski, the chief technology officer (CTO) and chief financial officer (CFO) at Denali, will deliver a keynote speech at next week’s International Symposium on Quality Electronic Design (ISQED), scheduled Tuesday, March 23rd at the DoubleTree Hotel in San Jose, CA.

WHO: Mark Gogolewski, CTO & CFO at Denali Software

WHAT: “Beyond Endless Verification: Delivering High-Quality at Low Expense.” With design verification costs skyrocketing across the industry, Denali Software faced the same challenge when tackling the verification of their configurable controller for PCI Express, one of the most popular, yet complex, interface protocols. As a commercial provider of IP, quality could not be sacrificed. At the same time, the business model could not support a huge design and verification team, nor wait forever. In his keynote, Denali CTO Mark Gogolewski will center on how a small group of talented, highly motivated engineers was able to consistently deliver one of the industry’s most complex IP cores, reliably and on-time. For more information, visit: http://isqed.org/.

WHEN: Tuesday, March 23, 2010 – 9:45am – 10:15am

WHERE: DoubleTree Hotel, San Jose, California – Fir/Oak Salons

Pre-silicon Compliance and Interoperability Solution Accelerates System Design Verification Targeting Computing, Virtualization, and FCoE Products

SUNNYVALE, Calif., February 18, 2010 — Denali Software, Inc., today announced the industry’s first PureSpec-Ethernet verification intellectual property (VIP) product to support the preliminary 40/100 Gigabit(Gb) specification from the IEEE Ethernet Task Force and delivery to current networking and communication customers for use in deploying next-generation Ethernet products. The preliminary specification, which sends Ethernet frames at 40 and 100 gigabits per second, enables developers to take advantage of the increased bandwidth for advanced computing, virtualization, video on demand, Fibre Channel over Ethernet (FCoE), Network-Attached Storage (NAS), VoIP and video surveillance applications. Denali’s PureSpec-Ethernet VIP product provides a comprehensive coverage of the specification and can be integrated into any verification methodology, thus accelerating the pre-silicon design and verification of a variety of Ethernet devices and systems. Denali will be demonstrating its high-quality PureSpec solution for 40/100Gb Ethernet (GbE) design in Booth #1 at the Ethernet Technology Summit in San Jose, California, on February 24-5, 2010.

“Our collection of Ethernet VIP offerings have expanded to include support for 40 Gb/s and 100 Gb/s speeds, providing a further incentive to designers that were waiting on the sidelines for the maturation of the P802.3ba specification and ecosystem,” states Sanjiv Kumar, director, Verification Products at Denali Software. “Our comprehensive verification platform, experience, and support provide the optimal solution for device and system designers aiming to leverage the increased bandwidth features within the new protocol and develop advanced Ethernet marketplace offerings.”

Denali's PureSpec VIP software for the preliminary IEEE P802.3ba specification supports all aspects of the specification including block distribution, lane reordering, alignment insertion, alignment removal, alignment lock per lane, block synchronization per lane, lane deskew, auto-negotiation, as well as the optional sub-layer forward error correction (FEC).

About PureSpec Ethernet Verification IP
Denali’s PureSpec is the most widely used verification IP product for verifying compliance and compatibility of Ethernet designs. All PureSpec products are directly integrated into all popular EDA languages and verification environments including: Verilog, SystemVerilog, VHDL, C/C++, SystemC, 'e', OpenVERA. Quality, completeness and seamless integration with all modern verification environments, e.g., OVM, VMM, eRM, etc., make PureSpec the solution of choice for functional verification and interoperability validation of Ethernet designs. A solid product platform, dedicated customer support, and unmatched EDA modeling and verification expertise make PureSpec Ethernet the best-in-class verification IP solution. Visit: https://www.denali.com/en/products/purespec_gige.jsp for more information about PureSpec-Ethernet.

Longstanding Native Integration of Denali Verification Portfolio with OVM on Mentor’s Questa Verification Platform Provides Verification Engineers Best-in-Class Tools

SUNNYVALE, Calif., Feb. 10, 2010 – Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced a joint Mentor-Denali on-demand webcast about verification maximizing productivity in an Open Verification Methodology (OVM) environment by leveraging Denali PureSpec™ features. The webcast provides a high-level view of several OVM features such as: testbench separation, flexible component instantiation, configurability, sequence stimulus, and TLM communications as well as the implementation of these elements with the industry-standard PureSpec solution for predictable protocol verification.

“The accelerated adoption of OVM has led to increased demands for advanced information to derive the most from OVM,” said Dennis Brophy, director of strategic business development at Mentor Graphics. “Collaborating with Denali has allowed us to put in place an educational webcast that highlights the industry’s most extensive OVM-based portfolio of robust verification solutions along with our best-in-class design and verification environment.”

Denali’s SystemVerilog VIP solutions support an expansive collection of the latest interface and memory technologies, including PCI Express 3.0, SATA, USB 3.0, DDR3, and NAND Flash, enabling seamless integration with OVM and Questa verification platform for accelerated verification closure. Denali’s PureSpec™ and MMAV have supported OVM since the 1.0 specification. Additionally, PureSpec’s transactors, sequence libraries, and scoreboard features can be seamlessly integrated in any OVM-based verification environment to minimize risks improve design quality.

“AppliedMicro values working with leading IP providers, such as Denali, who can provide high-quality products to help us achieve our design requirements in the most cost-effective manner,” said Amal Bommireddy, vice president of engineering at AppliedMicro. “In order to get to market quickly with lower risk of integration errors, AppliedMicro chose Denali verification IP architected for seamless integration into our advanced SystemVerilog design and verification methodology. Denali's products' performance and integration gives us confidence that our end-products will properly interoperate with these industry standard interfaces.”

“We have a large number of customers who use our solutions in an OVM environment to ensure that their designs are fully validated,” said Sanjiv Kumar, director, technical marketing of IP products for Denali. “We are pleased to provide this educational webcast with Mentor to help our mutual customers leverage these features to increase their design and verification productivity.”

About Denali’s Verification IP Portfolio
Denali’s best-in-class, standards-based VIP solutions provides more than 500 companies worldwide the latest technology to design and verify complex chip interfaces for communication, consumer, and computing products. Denali's MMAV and PureSpec products are part of a comprehensive VIP portfolio for predictable compliance of memories and protocol interfaces. Denali’s VIP seamlessly integrates into various testbenches, languages, simulators, and is compliant with popular advanced verification methodologies. For more details, visit: www.denali.com/purespec and www.denali.com/mmav.

Denali's Broad Portfolio of Predictable Protocol Verification IP Products and Protocol Expertise Key Deciding Factors

SUNNYVALE, Calif., Feb. 4, 2010 — Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Marvell, a world leader in the development of storage, communications, and consumer silicon solutions, has signed an expanded business agreement that establishes Denali as an IP partner thus enabling a company-wide adoption of Denali's comprehensive line of verification IP (VIP) products to speed the design and verification of Marvell's future products for various applications. Marvell is using Denali’s PureSuite™ compliance suite, PureSpec™ and MMAV™ for functional verification of complex interface protocols such as: PCIe 3/2/1, USB 3/2, Ethernet, and SATA 3/2. By utilizing Denali’s products, Marvell’s design and verification teams can improve their time-to-market with lower risk of integration errors, integrate the IP seamlessly into their design and verification methodology and deliver the confidence that their end-products are designed to properly interoperate with these industry standard interfaces.

“Our leadership in technology innovation and successful delivery of highly complex SoCs and our track record of first-silicon successes are complemented by Denali and their ability to meet a variety of our product requirements,” said Dr. Pantas Sutardja, vice president and Chief Technology Officer and Chief Research and Development Officer at Marvell. “Denali has provided impressive design tool quality, performance and protocol expertise. They have demonstrated their protocol expertise with the latest specifications and we look forward to our continued collaboration with Denali as we develop our next-generation applications.”

“Denali understands the important technical challenges facing Marvell's design methodology for chip and system development. Our verification IP products, which include support for the latest PCIe, USB, SATA and Ethernet specifications help to ensure that Marvell will be able to meet aggressive schedules for their designs,” said David Lin, vice president of Marketing at Denali Software. "Our industry leading products will help Marvell's SoC designers accelerate their design time, meet their performance goals and help them achieve a competitive advantage.”

About Denali VIP Solutions
Denali’s best-in-class, standards-based verification IP (VIP) solutions provides more than 500 companies worldwide the latest technology to design and verify complex chip interfaces for communication, consumer, and computing products. Denali's MMAV™ and PureSpec™ products are part of a comprehensive VIP portfolio for predictable compliance of memories and protocol interfaces. Denali’s VIP seamlessly integrates into various testbenches, languages, simulators, and is compliant with popular advanced verification methodologies (e.g., OVM, VMM, eRM, etc.). For more info about these products, visit www.denali.com/purespec.