SAN JOSE, Calif., 17 Jun 2010

Cadence Design Systems, Inc. (Nasdaq: CDNS), a leader in global electronics design innovation, today announced that it has successfully completed the acquisition of Denali Software, Inc., a Sunnyvale, Calif.-based provider of electronic design automation (EDA) software and intellectual property (IP).

Tightly aligned with Cadence’s strategy to deliver on the EDA360 vision for applications-driven system design, Denali’s product portfolio includes industry leading Memory Models, Design IP and Verification IP. The completion of this transaction enables Cadence to accelerate its EDA360 execution and expands the company’s solution portfolio to provide efficient, cost-effective system component modeling and IP integration.

“We envision a way forward for the electronics industry, called EDA360, that addresses the emerging shift to applications-driven systems and SoC Realization,” said Lip-Bu Tan, president and chief executive officer, Cadence. “Our customers’ needs are changing, and EDA providers must respond with their own EDA360 initiatives. The acquisition of Denali, and its world-class design and verification IP and memory models, gives Cadence a significant, first-mover advantage as we execute our strategy.”

The Denali team, including founders Sanjay Srivastava and Mark Gogolewski, will report to Nimish Modi, senior vice president, research and development, Front End Group, Cadence.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design, verify, and implement advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, California, with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

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High-Quality Databahn DDR3/2 SDRAM Controller and DFI-Compliant Synthesizable GHz PHY Utilized in Various eMPUs for Communication, Display and Networked Devices

SUNNYVALE, Calif., June 9, 2010 – Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that STMicroelectronics, a global leader in developing and delivering SoC and semiconductor solutions, has integrated Denali’s configurable Databahn® DDR3/DDR2 SDRAM multiport memory controller IP and DFI-compliant Synthesizable GHz PHY IP as a baseline solution for the Structured Processor Enhanced Architecture (SPEAr®) embedded microprocessor platform. STMicroelectronics’ engineers were able to meet their specific design requirements and add configurability to their chips by leveraging the Databahn controller and PHY IP for their SPEAr family of microprocessors (SPEAr600 and later). The new SPEAr1300 product line architecture provides substantial breakthrough in computing power and connectivity for networked devices and will be used for communication, display and control applications.

“We selected Denali because of its established leadership in delivering high-quality IP and PHY technology, which has been silicon-proven in a wide range of our high-performance SoC designs,” remarks Stefano Ravaglia, SoC R&D director at STMicroelectronics. “Our new-generation SPEAr family of embedded microprocessor technologies targets many of today’s computing and connectivity requirements. Denali’s Databahn controller IP and PHY can be easily implemented in our advanced HCMOS process technologies providing the marketplace with the optimal solutions to streamline embedded SoC designs.”

STMicroelectronics’ SPEAr family of microprocessors targets embedded-control applications across market segments from computer peripherals and communications to industrial automation. These devices allow equipment manufacturers to develop complex yet flexible digital engines with remarkable time and cost savings during the design cycle. STMicroelectronics’s SPEAr multi-application chips are manufactured in state-of-the-art, low-power 90, 65, and 55nm HCMOS (high-speed CMOS) process technologies and provide high levels of computing power and connectivity.

“As the leading provider in connectivity IP, we continue to provide customers such as STMicroelectronics with comprehensive, high-quality solutions that reduce design risk and enable them to develop complex chips on schedule,” commented Marc Greenberg, director, Technical Marketing at Denali Software. “We appreciate ST’s trust in Denali and welcome the opportunity to help them ramp their SoC designs to volume production faster.”

About Databahn DDR SDRAM Solutions
Denali’s Databahn configurable, high-performance memory controller ensures compatibility with all the latest high-speed SDRAM technologies, including the many DDR3/2 and LPDDR2/1 devices offered by all major memory vendors. The Databahn controller IP has been proven in all major commercial process technology nodes. Databahn controllers are DFI-compliant (DFI is the industry’s standard interface between memory controllers and PHYs), they are highly configurable, and they are easy-to-integrate into a chip design, making them an appropriate match for a wide range of system architectures. For more info, visit: www.denali.com/dram.