Databahn Configurable DDR2/3 Controller Delivers Best Solution for
High-End Video Applications

SUNNYVALE, Calif., April 27, 2010 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Pixelworks (NASDAQ: PXLW), an innovative provider of powerful video and pixel processing technology, has selected Denali’s Databahn™ DFI-compliant DDR3/2 memory controller IP for its upcoming IC designs targeting innovative products for the advanced video display market. Databahn enables Pixelworks’ developers to meet performance goals in their high-volume SoCs for professional and consumer product designs.

“Denali’s DDR controller IP solution allows Pixelworks to meet the design requirements of our OEM customers,” said John Lau, vice president, China General Manager of Pixelworks. “Denali’s DDR memory controller is unmatched in performance and represents the highest quality IP solution in the industry. Denali’s expertise and reputation were key factors in our decision to use their solution to aid us in addressing higher speed timing closure issues.”

The Databahn product provides a comprehensive infrastructure for configuring, analyzing, and generating the optimal memory controller for a given customer application. Denali’s Databahn DDR-SDRAM memory controllers offer a powerful, multi-port solution with configurable features and functionality to satisfy system performance requirements in terms of bandwidth, latency, and power. In addition, the Databahn memory controller reduces the required effort needed to integrate with DDR PHYs by supporting the latest version of the industry-standard DDR PHY Interface (DFI) specification.

“Consumer SoCs require specialized DDR memory systems that can address performance, quality, and time-to-market,” said Marc Greenberg, director, Technical Marketing of IP products for Denali. “The Databahn DDR controller solution provides optimal performance while enabling flexible power management schemes for a variety of video, broadband, and network displayed applications. We are pleased to be working with Pixelworks and look forward to helping them meet their aggressive time-to-market schedules as they develop and deliver their innovative new processors for high-end digital video applications.”

About Databahn DDR Memory Solutions
Denali’s Databahn DDR-SDRAM memory solutions ensure compatibility with all the latest high-speed memory technologies, including the many DDR2, DDR3, and LP-DDR2 devices from all major memory vendors, and supports all vendor process nodes. Databahn controllers are DFI compliant and highly configurable, enabling an opportune match for a wide range of system architectures. For more info, visit: www.denali.com/dram.

LPDDR1-SDRAM Controller and PHY Solution Enables 30 Percent Power Savings For Pocket TVs and Portable Media Players

SUNNYVALE, Calif., April 14, 2010 — Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Augusta Technology USA, a mobile digital solutions company, has selected Denali’s Databahn™ LPDDR1-SDRAM controller and PHY intellectual property (IP) products for incorporation into its latest processor, designed using TSMC’s Low Power (LP) process technology. The low-power processor solution enables mobile manufacturers to cost-effectively incorporate digital broadcast TV reception and other popular multimedia features into various portable devices such as cellular phones, portable media players, pocket TVs, smartphone PDAs, and vehicle media centers. Augusta’s engineers are using the unique power-saving features available in Denali’s LPDDR controller and PHY to achieve optimal system-level performance for the DRAM subsystem in Augusta’s processor design.

“As a provider of leading-edge mobile digital solutions, we are always looking to take advantage of the latest advances in low-power technologies,” said Aki Shohara, CTO at Augusta Technology USA. “Our engineers who have extensive and successful silicon design experience for mobile solutions, particularly with respect to power-saving optimization, selected Denali’s Databahn controller and PHY for our next mobile chip after careful evaluation. Denali’s high-quality LPDDR controller, PHY solutions and domain expertise were key factors in the selection to achieve our design requirements and to meet our time to market goals.”

The low-power features of Denali’s Databahn DRAM controller and memory PHY allow mobile systems to manage memory power usage either automatically or manually, whichever best suits the overall system design and power/performance goals. Databahn’s high-performance algorithms improve memory utilization. When combined with low-power IC process technology, systems can extract high-bandwidth performance from DRAM subsystems while operating them at low power. The PHY incorporates a digital delay locked loop (DLL) that reduces power consumption while still achieving high-performance design goals. In addition, IC designers find the PHY’s DLL easy to implement in silicon. The PHY’s low-power architecture combined with the memory controller’s intelligent management of the low-power modes built into commercial DDR memory cuts memory-subsystem power consumption by 30%. These advanced DRAM-management technologies and more will be highlighted at the upcoming MemCon event, “Roadmap: GHZ DDR3 and Beyond,” on July 28th, in Santa Clara, CA.

“Next-generation mobile SoCs that incorporate specialized DDR memory systems must deliver low-power features with very high-quality and within tight market windows,” states Marc Greenberg, director, technical marketing of IP products for Denali Software. “Our Databahn controller and PHY IP products not only provide optimal configurability and quality, but also incorporate flexible power-management options for a variety of next-generation portable digital television applications. We are pleased to have been able to work with Augusta Technology and help them meet their aggressive time-to-market schedules.”

About Databahn DDR Memory Solutions
Together, Denali's Databahn DDR controller and PHY constitute a complete solution that’s ready to be integrated into SoCs and ASICs. They ensure compatibility with all the latest high-speed, low-power memory technologies. This combination supports all memory component specifications, including all the latest DDR3/2/1 and LPDDR2/1 devices from all major memory vendors and support for all vendor process nodes. The PHY is configurable for data width, ECC, low power, and other options, and is delivered to match the unique requirements of a specific DDR application. For more info, visit: www.denali.com/databahn.