Link: http://gabeoneda.com/news/achieving-verification-reduction

At last week's International Symposium on Quality Electronic Design (ISQED), Mark Gogolewski, Denali CTO, delivered a keynote speech addressing the design and verification costs associated with high-quality design and detailed one small team's approach to consistently deliver one of the industry's most complex IP cores, reliably and on-time.

Below, Mark Gogolewski recaps his keynote in this interview with EDA Cafe.

Collaboration Springs High-Quality DDR-SDRAM C-Based Models for Enhanced System-Level Simulation and Performance Analysis

SUNNYVALE, Calif., Mar. 24, 2010 – Denali Software, Inc., a leading provider of intellectual property (IP) and electronic design automation (EDA) software, and Carbon Design Systems today announced a collaboration to provide designers with cycle-accurate models of Denali’s configurable Databahn™ DDR SDRAM controller IP for virtual platforms. Databahn IP models are available today for use with leading system simulation environments (including Carbon SoC Designer, CoWare Platform Architect, and OSCI SystemC) to perform architectural analysis, validate system performance, and perform hardware/software integration prior to silicon.

“We are extremely pleased to have Denali join our growing IP community,” stated Bill Neifert, vice president of Business Development at Carbon. “Our customers are using Denali’s high-performance Databahn DDR-SDRAM IP to architect some of the world’s most complex system on chip (SoC) designs. Adding Databahn DDR memory interface models to our IP offerings gives our mutual customers the ability to leverage the advanced capabilities of the platform across more of their designs.”

DDR SDRAM plays a critical role in overall system performance in a variety of applications including consumer, communications, and computing. This collaboration delivers 100% cycle-accurate models of this vital IP to the engineers who need it most: architects making critical performance tradeoffs and firmware developers debugging presilicon software. Cycle-accurate models are available immediately from Carbon Design Systems for all SDRAM memory interface IP in the Databahn portfolio, including support for the latest DDR3, DDR2, and LPDDR2 specifications.

“Denali is committed to expanding the ecosystem around our broad range of high-quality controller IP to ease our customers’ design process,” said Marc Greenberg, director, Technical Marketing at Denali Software. “Partnering with Carbon to make models of our DDR SDRAM controller cores available in SoC Designer and other virtual environments gives our customers access to a valuable platform to perform architectural exploration, optimize system performance, and debug complex firmware issues earlier and more accurately than previously possible.”

About Databahn DDR and PHY Solution
Denali’s Databahn DDR-SDRAM controller and synthesizable PHY IP is a complete solution ready to be integrated into SoCs and ASICs which interface with DDR memories. Each controller and PHY is delivered to match the unique requirements of the customer’s DDR application. These are configurable for data width, ECC, low power, and many other options, and supports DDR1/2/3 and LP-DDR1/2 devices. For more information about Databahn DDR-SDRAM and PHY solution, visit: http://www.denali.com/dram.

Link: http://www.edn.com/blog/1690000169/post/850053485.html??text=isqed

Industry Executive Discusses Achieving High-Quality Design and Verification at Low Expense Amidst Today’s Skyrocketing Costs

SUNNYVALE, Calif., Mar. 18, 2010 – Denali Software, Inc., a leading provider of intellectual property (IP) and electronic design automation (EDA) software, today announced that Mark Gogolewski, the chief technology officer (CTO) and chief financial officer (CFO) at Denali, will deliver a keynote speech at next week’s International Symposium on Quality Electronic Design (ISQED), scheduled Tuesday, March 23rd at the DoubleTree Hotel in San Jose, CA.

WHO: Mark Gogolewski, CTO & CFO at Denali Software

WHAT: “Beyond Endless Verification: Delivering High-Quality at Low Expense.” With design verification costs skyrocketing across the industry, Denali Software faced the same challenge when tackling the verification of their configurable controller for PCI Express, one of the most popular, yet complex, interface protocols. As a commercial provider of IP, quality could not be sacrificed. At the same time, the business model could not support a huge design and verification team, nor wait forever. In his keynote, Denali CTO Mark Gogolewski will center on how a small group of talented, highly motivated engineers was able to consistently deliver one of the industry’s most complex IP cores, reliably and on-time. For more information, visit: http://isqed.org/.

WHEN: Tuesday, March 23, 2010 – 9:45am – 10:15am

WHERE: DoubleTree Hotel, San Jose, California – Fir/Oak Salons