Archives for: February 2010
Pre-silicon Compliance and Interoperability Solution Accelerates System Design Verification Targeting Computing, Virtualization, and FCoE Products
SUNNYVALE, Calif., February 18, 2010 — Denali Software, Inc., today announced the industry’s first PureSpec-Ethernet verification intellectual property (VIP) product to support the preliminary 40/100 Gigabit(Gb) specification from the IEEE Ethernet Task Force and delivery to current networking and communication customers for use in deploying next-generation Ethernet products. The preliminary specification, which sends Ethernet frames at 40 and 100 gigabits per second, enables developers to take advantage of the increased bandwidth for advanced computing, virtualization, video on demand, Fibre Channel over Ethernet (FCoE), Network-Attached Storage (NAS), VoIP and video surveillance applications. Denali’s PureSpec-Ethernet VIP product provides a comprehensive coverage of the specification and can be integrated into any verification methodology, thus accelerating the pre-silicon design and verification of a variety of Ethernet devices and systems. Denali will be demonstrating its high-quality PureSpec solution for 40/100Gb Ethernet (GbE) design in Booth #1 at the Ethernet Technology Summit in San Jose, California, on February 24-5, 2010.
“Our collection of Ethernet VIP offerings have expanded to include support for 40 Gb/s and 100 Gb/s speeds, providing a further incentive to designers that were waiting on the sidelines for the maturation of the P802.3ba specification and ecosystem,” states Sanjiv Kumar, director, Verification Products at Denali Software. “Our comprehensive verification platform, experience, and support provide the optimal solution for device and system designers aiming to leverage the increased bandwidth features within the new protocol and develop advanced Ethernet marketplace offerings.”
Denali's PureSpec VIP software for the preliminary IEEE P802.3ba specification supports all aspects of the specification including block distribution, lane reordering, alignment insertion, alignment removal, alignment lock per lane, block synchronization per lane, lane deskew, auto-negotiation, as well as the optional sub-layer forward error correction (FEC).
About PureSpec Ethernet Verification IP
Denali’s PureSpec is the most widely used verification IP product for verifying compliance and compatibility of Ethernet designs. All PureSpec products are directly integrated into all popular EDA languages and verification environments including: Verilog, SystemVerilog, VHDL, C/C++, SystemC, 'e', OpenVERA. Quality, completeness and seamless integration with all modern verification environments, e.g., OVM, VMM, eRM, etc., make PureSpec the solution of choice for functional verification and interoperability validation of Ethernet designs. A solid product platform, dedicated customer support, and unmatched EDA modeling and verification expertise make PureSpec Ethernet the best-in-class verification IP solution. Visit: https://www.denali.com/en/products/purespec_gige.jsp for more information about PureSpec-Ethernet.
Longstanding Native Integration of Denali Verification Portfolio with OVM on Mentor’s Questa Verification Platform Provides Verification Engineers Best-in-Class Tools
SUNNYVALE, Calif., Feb. 10, 2010 – Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced a joint Mentor-Denali on-demand webcast about verification maximizing productivity in an Open Verification Methodology (OVM) environment by leveraging Denali PureSpec™ features. The webcast provides a high-level view of several OVM features such as: testbench separation, flexible component instantiation, configurability, sequence stimulus, and TLM communications as well as the implementation of these elements with the industry-standard PureSpec solution for predictable protocol verification.
“The accelerated adoption of OVM has led to increased demands for advanced information to derive the most from OVM,” said Dennis Brophy, director of strategic business development at Mentor Graphics. “Collaborating with Denali has allowed us to put in place an educational webcast that highlights the industry’s most extensive OVM-based portfolio of robust verification solutions along with our best-in-class design and verification environment.”
Denali’s SystemVerilog VIP solutions support an expansive collection of the latest interface and memory technologies, including PCI Express 3.0, SATA, USB 3.0, DDR3, and NAND Flash, enabling seamless integration with OVM and Questa verification platform for accelerated verification closure. Denali’s PureSpec™ and MMAV have supported OVM since the 1.0 specification. Additionally, PureSpec’s transactors, sequence libraries, and scoreboard features can be seamlessly integrated in any OVM-based verification environment to minimize risks improve design quality.
“AppliedMicro values working with leading IP providers, such as Denali, who can provide high-quality products to help us achieve our design requirements in the most cost-effective manner,” said Amal Bommireddy, vice president of engineering at AppliedMicro. “In order to get to market quickly with lower risk of integration errors, AppliedMicro chose Denali verification IP architected for seamless integration into our advanced SystemVerilog design and verification methodology. Denali's products' performance and integration gives us confidence that our end-products will properly interoperate with these industry standard interfaces.”
“We have a large number of customers who use our solutions in an OVM environment to ensure that their designs are fully validated,” said Sanjiv Kumar, director, technical marketing of IP products for Denali. “We are pleased to provide this educational webcast with Mentor to help our mutual customers leverage these features to increase their design and verification productivity.”
About Denali’s Verification IP Portfolio
Denali’s best-in-class, standards-based VIP solutions provides more than 500 companies worldwide the latest technology to design and verify complex chip interfaces for communication, consumer, and computing products. Denali's MMAV and PureSpec products are part of a comprehensive VIP portfolio for predictable compliance of memories and protocol interfaces. Denali’s VIP seamlessly integrates into various testbenches, languages, simulators, and is compliant with popular advanced verification methodologies. For more details, visit: www.denali.com/purespec and www.denali.com/mmav.
Denali's Broad Portfolio of Predictable Protocol Verification IP Products and Protocol Expertise Key Deciding Factors
SUNNYVALE, Calif., Feb. 4, 2010 — Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Marvell, a world leader in the development of storage, communications, and consumer silicon solutions, has signed an expanded business agreement that establishes Denali as an IP partner thus enabling a company-wide adoption of Denali's comprehensive line of verification IP (VIP) products to speed the design and verification of Marvell's future products for various applications. Marvell is using Denali’s PureSuite™ compliance suite, PureSpec™ and MMAV™ for functional verification of complex interface protocols such as: PCIe 3/2/1, USB 3/2, Ethernet, and SATA 3/2. By utilizing Denali’s products, Marvell’s design and verification teams can improve their time-to-market with lower risk of integration errors, integrate the IP seamlessly into their design and verification methodology and deliver the confidence that their end-products are designed to properly interoperate with these industry standard interfaces.
“Our leadership in technology innovation and successful delivery of highly complex SoCs and our track record of first-silicon successes are complemented by Denali and their ability to meet a variety of our product requirements,” said Dr. Pantas Sutardja, vice president and Chief Technology Officer and Chief Research and Development Officer at Marvell. “Denali has provided impressive design tool quality, performance and protocol expertise. They have demonstrated their protocol expertise with the latest specifications and we look forward to our continued collaboration with Denali as we develop our next-generation applications.”
“Denali understands the important technical challenges facing Marvell's design methodology for chip and system development. Our verification IP products, which include support for the latest PCIe, USB, SATA and Ethernet specifications help to ensure that Marvell will be able to meet aggressive schedules for their designs,” said David Lin, vice president of Marketing at Denali Software. "Our industry leading products will help Marvell's SoC designers accelerate their design time, meet their performance goals and help them achieve a competitive advantage.”
About Denali VIP Solutions
Denali’s best-in-class, standards-based verification IP (VIP) solutions provides more than 500 companies worldwide the latest technology to design and verify complex chip interfaces for communication, consumer, and computing products. Denali's MMAV™ and PureSpec™ products are part of a comprehensive VIP portfolio for predictable compliance of memories and protocol interfaces. Denali’s VIP seamlessly integrates into various testbenches, languages, simulators, and is compliant with popular advanced verification methodologies (e.g., OVM, VMM, eRM, etc.). For more info about these products, visit www.denali.com/purespec.
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