Advanced Phase PHY Incorporates An Innovative Over-Sampling Approach Achieving Rapid Implementation Times for High-Performance Memory Systems

SUNNYVALE, Calif., December 10, 2009 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today revealed a new phase PHY technology for DDR SDRAM physical interfaces, delivering memory system performance up to 1066 MHz clock speeds (or DDR-2133 data rates) on 65-nanometer foundry process nodes or lower. Denali’s phase PHY technology applies a high-speed oversampling architecture paired with per-bit data capture and calibration mechanism to achieve GHz clock rates. This third-generation DDR PHY technology is delivered as a fully-synchronous design which benefits design teams with the configurability needed to satisfy their physical implementation requirements.

As DDR SDRAM devices reach 2133 Mbps data rates, bit-to-bit skews within the data lanes become significant fractions of the data window. Denali’s oversampling architecture employs an 8- or 16-phase lock loop (PLL) and performs pattern matching to determine the correct data sample points for DDR data for each transaction. By managing the data capture on a per-bit basis (rather than on a per-byte basis), Denali’s PHY reliably closes timing at 1066 MHz clock rates. Furthermore, differences in the routing of data and data strobe signals are calibrated in the silicon eliminating the need for time-consuming hand layout. The fully-synchronous design provides flexibility for floorplanning, pin placement, and power routing and uses standard EDA toolsets to easily realize a reliable implementation.

“The continued demand for increased bandwidth in various internet and electronic applications is driving the need for DDR3 technology and for the ability to support data rates up to 2133 Mbp/s,” states Mike McKeon, director of PHY IP at Denali. “Our DDR phase PHY is cutting-edge technology, delivering effective management of GHz clock speeds and a perfect match for our customers’ specific design implementation needs.”

About Databahn DDR PHY Solutions
Denali’s Databahn DDR PHY is a complete solution ready to be integrated into SoCs and ASICs which interface with DDR memories. Each PHY is delivered to match the unique requirements of the customer’s DDR application. The PHY is configurable for data width, ECC, low power, and many other options, and supports DDR3/2 and LP-DDR1/2 devices. For more info, visit: www.denali.com/ddrphy, Databahn PHY Frequently Asked Questions, and Animated Guide to Denali DDR PHY.

High-Quality Verification IP Portfolio Accelerates Design and Verification
Of High-Performance Processors

SUNNYVALE, Calif., Dec. 8, 2009 — Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Ubicom, a leading provider of networking and multimedia processor solutions, has extended its relationship with Denali, taking full advantage of its advanced protocol verification technology and services. Ubicom has selected Denali’s MMAV™ and PureSpec™ verification IP (VIP), which support high-speed communications and peripheral protocols, to aid in the design and verification of their media and network processors. Denali’s MMAV and PureSpec fortifies Ubicom’s designers with a predictable protocol verification IP solution to meet their design requirements and lower integration risk, ensuring interoperability with new products.

“Our hardware and software innovations enable multimedia and networking products that ensure a high-quality user experience and unprecedented ease of use,” states Jon Gibbons, vice president of VLSI Engineering at Ubicom. “Denali has consistently provided robust, high-quality verification IP solutions and reaffirmed their superb industry reputation for protocol expertise. We are confident that their solutions will continue to enable our designers to take advantage of the latest protocol features and quickly create innovative products with less risk and improved time-to market.”

As a leading provider of networking and multimedia processor solutions, Ubicom delivers communications and media processor and software platforms that address the unique demands of real-time interactive applications and multimedia content delivery in the digital home. Ubicom will utilize Denali’s PureSpec and MMAV products in their in their next generation of multimedia and network processors.

“SoC design and verification teams look to Denali to provide the industry’s best-in-class verification solutions to accelerate the pre-silicon design and verification of protocol applications,” states Sanjiv Kumar, director, Verification Products at Denali Software. “We value Ubicom’s trust in Denali and are confident that our predictable protocol verification IP will minimize risks and increase design productivity.”

About Denali’s Verification IP Portfolio
Denali’s best-in-class, standards-based verification IP (VIP) solutions provides more than 500 companies worldwide the latest technology to design and verify complex chip interfaces for communication, consumer, and computing products. Denali's MMAV and PureSpec products are part of a comprehensive VIP portfolio for predictable compliance of memories and protocol interfaces. Denali’s VIP seamlessly integrates into various testbenches, languages, simulators, and is compliant with popular advanced verification methodologies (e.g., OVM, VMM, eRM, etc.). For more details, visit: www.denali.com/purespec and www.denali.com/mmav.