Best-in-Class Solutions Speed Design-to-Silicon Success of PCI Express Technology

SUNNYVALE, Calif., Oct. 20, 2009 — Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Cray has adopted Denali Databahn™ PCI Express (PCIe) controller core and PureSpec™ verification IP (VIP), which support the latest PCIe 3.0 specifications from the PCI-SIG. The 16-lane PCIe 3.0 controller from Denali can deliver 128 GT/s of raw bandwidth, surpassing a 100G Ethernet interface. This is equivalent to transferring a full 3-hour high-definition movie file in under one second.

“Our systems are deployed in mission critical applications and require superior performance, scalability, and reliability. After examining the available solutions in the industry, it was clear that Denali was more than capable of delivering a PCI Express 3.0 controller with the critical features that we needed,” states Peg Williams, senior vice president of research and development at Cray. “Not only has Denali met our functional and performance requirements, but their reputable technology, verification expertise and strong customer reputation made them a valued supplier.”

As a global leader in supercomputing, Cray provides supercomputing, storage and data management technologies to government, industry and academia. Cray technology enables scientists and engineers to achieve remarkable breakthroughs by accelerating performance, improving efficiency and extending the capabilities of their most demanding applications. Last year, the Cray XT5 system, nicknamed “Jaguar” and located at the Oak Ridge National Laboratory, was number two on the list of the World's Top 500 Supercomputers.

“Denali continues to provide the industry’s highest-quality IP solutions for PCIe technology, which enables our customers, such as Cray, to reduce their design risk and enable them to develop complex projects on schedule,” remarks Ashwin Matta, Director of PCIe Core Technology for Denali Software. “We value Cray's trust in Denali and are confident that our design and verification IP products will accelerate their design time, meet their performance goals and help them achieve a competitive advantage.”

About Databahn PCI Express Solutions
Denali's Databahn PCIe cores and PureSpec verification IP software for PCI Express provide full support of the latest capabilities, such as: Internal Error Reporting, ID Based Ordering, TLP Processing Hints, Optimized Buffer Flush/Fill, Atomic Operations, Re-Sizable BAR, Extended TAG Enable, Dynamic Power Allocation, and Latency Tolerance Reporting. For more info about Databahn and PureSpec, visit www.denali.com/pcie.

High-Quality, Configurable DDR PHY Deployed in Video Processing Chips For AV Receivers and Blu-ray Players

SUNNYVALE, Calif., October 15, 2009 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Anchor Bay, a leading supplier of video-processing semiconductors (ASICs) and systems, has successfully taped out its ABT2015 chip utilizing Denali’s next-generation Databahn™ DDR PHY solution in 65-nanometer(nm) Common Platform™ process technology offered by IBM, Chartered Semiconductor Manufacturing Ltd., and Samsung Electronics Co., Ltd. Denali’s Databahn solution enabled Anchor Bay’s developers to meet optimal performance design requirements in their high-volume SoCs for video processing semiconductor products that advancing the optimum home theater experience.

“The superior quality produced by our advanced video processing algorithms places high demands on the performance of the DDR interface,” said Satish Iyengar, Director, Semiconductor Engineering at Anchor Bay. “Denali’s Databahn DDR synthesizable PHY was configurable, high-quality and delivered what no other vendor could within our time-to-market constraints. Denali’s demonstrated the industry’s best expertise and customer support and their PHY solution helped address our performance and design requirements.”

Anchor Bay’s ABT2015 chip is ideally suited for video processing functions in A/V receivers, Blu-ray player recorders, and digital displays. The chip includes all of Anchor Bay’s award winning Video Reference Series™ technologies, including PReP™ (Progressive ReProcessing), Precision Deinterlacing™ , Precision Video Scaling™, Mosquito Noise Reduction and Picture Enhancement. The ABT2015 supports HDMI 1.3 Deep Color and is pin-out compatible with the ABT2010.

Anchor Bay used Denali’s DFI-compliant PHY with their own in-house memory controller, reducing the integration effort by using this industry standardized interface. Denali’s Databahn DDR PHY product offers a powerful, feature-rich technology for creating and implementing DDR PHY without the need for custom layout services. The DDR-PHY provides a configurable platform for specifying the unique functional and physical PHY characteristics for a given customer application. This specification results in a custom synthesizable design and scripts for constraints and timing validation suitable for automated place and route implementation tools.

“Consumer SoCs require specialized DDR memory systems that must address performance, quality, and time-to-market,” said Mike McKeon, director, PHY Technology for Denali. “The Databahn DDR PHY solution provides optimal configurability and quality while enabling flexible power management schemes for a variety of next-generation digital television and high-definition digital video applications. We are pleased to have been able to work with Anchor Bay and help them meet their aggressive time-to-market schedule.”

About Databahn DDR PHY Solutions
Denali’s Databahn DDR PHY is a complete solution ready to be integrated into SoCs and ASICs which interface with DDR memories. Each PHY is delivered to match the unique requirements of the customer’s DDR application. The PHY is configurable for data width, ECC, low power, and many other options, and supports DDR1/2/3 and LP-DDR1/2 devices. For more info, visit: www.denali.com/dram.