Archives for: July 2009
Protocol Expertise Provides Foundation for Verification Planning and Exploration
SUNNYVALE, Calif., July 23, 2009 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced the availability of the extended PureSpec™ verification IP solution with planning and protocol exploration capabilities, plus seamless integration into 3rd party verification planners, such as Synopsys® VMM Planner. These predictable protocol verification features enable design and verification engineers to accelerate and achieve verification closure. Visit the Denali booth (#1424) at DAC for a live VMM Planner demonstration.
“The new release of Denali’s PureSpec addresses the expertise and predictability gap in the verification of complex protocols,” states Dr. Ambar Sarkar, Chief Verification Technologist at Paradigm Works. “They have been leading the industry with their comprehensive verification IP solutions for protocols, like PCI Express and USB, and these breakthrough capabilities will certainly increase adoption.”
Denali’s PureSpec verification solution generates a customized and comprehensive hierarchical test plan based on protocol specifics and design parameters. This planning feature provides design and verification engineers with an unbiased and complete test plan in standard formats, offering a transparent and objective measurement scale.
The protocol explorer within PureSpec provides visibility into protocol concepts and objects, instead of simple wave forms. This context sensitive and protocol-aware debugger facilitates the reporting of state machines and properties, and back tracing of data packets and protocol events, thus shortening the debugging cycle times.
Additionally, PureSpec enables seamless integration with advanced verification methodologies and third party planners enabling automated verification and back-annotation of the coverage data to the test plan. This tight integration closes the loop and substantially improves the predictability of the verification process. Denali’s CTO, Mark Gogolewski, will present at the Synopsys Interoperability Breakfast on Wednesday, July 29, “Peace, Love and Interoperability: Improving Quality & Productivity with Verification & Custom Design Standards” which will highlight PureSpec’s integration with VMM Planner.
“Language and methodology standards have a major impact on customers’ verification interoperability and productivity,” said Yatin Trivedi, director of standards at Synopsys. “Denali’s support for the VMM methodology, including their new verification plans compatible with Synopsys’ VMM Planner, benefits the growing VMM ecosystem.”
“Protocol expertise plays an important role when addressing today’s complex verification challenges,” states Sanjiv Kumar, director, Verification IP products at Denali. “Our PureSpec product enables automated validation of a protocol interface through high-quality test plans, sequence and assertion libraries and BFM via any coverage driven methodology. Denali PureSpec further delivers a powerful capability for protocol-aware exploration and intuitive debugging.”
About Denali PureSpec
PureSpec is a predictable verification solution for protocol compliance and enables verification planning and coverage-driven verification closure. PureSpec verification solution includes a configurable bus functional model, protocol monitor, and complete assertion library for all components in the topology. PureSpec additionally provides an integrated data generation engine to help drive defined, pseudo-random bus traffic at all layers. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design. For more product information, visit: www.denali.com/purespec.
Denali PureSpec Accelerates Design and Verification of New Generation of USB Chip Sets
SUNNYVALE, Calif., July 23, 2009 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced six top-ten semiconductor customers have taken delivery of Denali PureSpec™ verification IP (VIP) solution, based on the latest USB 3.0 specification from the USB Implementer’s Forum (USB-IF), for use in next-generation chip designs. Denali's PureSpec solution was selected to accelerate the pre-silicon design and verification of a variety of USB 3.0 host controllers, SATA bridges and USB 3.0 devices targeting end applications in computing, external hard drives, digital cameras and camcorders.
“SoC design and verification teams continually look to Denali for predictable protocol verification IP to minimize risks and increase design productivity,” states Sanjiv Kumar, director, Verification Products at Denali Software. “We are pleased with the rapid market adoption our PureSpec VIP solution for the SuperSpeed USB 3.0. We anticipate our lead customers will announce their USB 3.0 based products later this year.”
As the industry’s first-to-market USB 3.0 solution, Denali's PureSpec VIP product provides full support of the USB 3.0 specification with features including: full timing and bus functional modeling of host, device and hub across all protocol layers, power management support, backwards compatibility to USB 2.0, and complete USB enumeration. Access more detailed info about PureSpec USB 3.0 VIP features and request an evaluation at: www.denali.com/usb3.
About PureSpec
PureSpec is a predictable verification solution for protocol compliance and enables verification planning and coverage-driven verification closure. PureSpec verification solution includes a configurable bus functional model, protocol monitor, and complete assertion library for all components in the topology. PureSpec additionally provides an integrated data generation engine to help drive defined, pseudo-random bus traffic at all layers. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design. For more information about PureSpec USB 3, visit: www.denali.com/usb3.
Founders and Design Automation Conference Exhibitors Atrenta, Denali, SpringSoft Urge Community to Attend DAC, “Show Your Love”
SAN JOSE, Calif., July 22, 2009 – The DAC Fan Club, founded by Atrenta, Denali and SpringSoft, urges attendees of the upcoming 46th Design Automation Conference (DAC), and those not able to attend this year to share their favorite DAC story and explain why they love DAC at I Love DAC.
What started as an ad-hoc effort by Atrenta, Denali and SpringSoft to offer 600 week-long DAC exhibit passes free of charge has evolved into a true online fan club where the design automation community can connect and share experiences. Each company invites DAC attendees to stop by their booth (Atrenta #1528, Denali #1424, SpringSoft #3367) to pick up an official fan club button, wear it during DAC and win an iPod touch if you are spotted with it on.
“Let’s face it, DAC is the focal point for our industry. With the vast momentum and innovation that exists within the EDA industry, the I Love DAC site provides a place for people to share and reflect on the many experiences that the annual event has on our lives,” said Mike Gianfagna, vice president of marketing for Atrenta. “Atrenta is pleased to be a part of the DAC Fan Club and I hope everyone will join the community and contribute to the collective memory of show.”
“It is at DAC that I most feel part of a real EDA community,” said Scott Sandler, vice president of corporate marketing for SpringSoft, and president of SpringSoft USA. “We hope that the DAC Fan Club gives people around the world a way to tap into that feeling for years to come.”
“Our goal is that this online community not only serve as another common thread that binds us all together, but in addition stimulates and encourages others to become more involved in DAC and the EDA industry,” remarked David Lin, vice president of marketing for Denali.
This year’s DAC will be held July 26-31 at the Moscone Center in San Francisco. For details or to register, visit: www.dac.com.
About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. For more information, visit www.atrenta.com. Atrenta, Right from the Start!
About SpringSoft
SpringSoft, Inc. is a global supplier of specialized automation technologies that accelerate engineers during the design, verification and debug of complex digital, analog and mixed-signal ICs, ASICs, microprocessors, and SoCs. Its award-winning product portfolio features the Novas™ Verification Enhancement and Laker™ Custom IC Design solutions used by more than 400 of today's leading IDM and fabless semiconductor companies, foundries, and electronic systems OEMs. Headquartered in Hsinchu, Taiwan, and San Jose, California, SpringSoft is the largest company in Asia specializing in IC design software and a recognized industry leader in customer service with more than 400 employees located in multiple R&D sites and local support offices around the world. For more information, visit www.springsoft.com.
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Atrenta, the Atrenta logo, SpyGlass, and Early Design Closure are registered trademarks of Atrenta, Inc. Atrenta, Denali and SpringSoft acknowledge trademarks or registered trademarks of other organizations for their respective products and services.
