Archives for: September 2008
09/23/08
Denali Software Design and Verification IP Adopted By Siverge Networks to Accelerate ASIC Design for Wireless Solution Providers
Denali’s Configurable DDR2/3 DRAM, PHY, and Verification IP Products Enable
Siverge Networks to Optimize Performance in Network Convergence Processor
SUNNYVALE, Calif., September 23, 2008 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Siverge Networks, a fabless semiconductor company focused on the packet evolution in carrier networks, has adopted Denali’s Databahn™ DDR2/3 memory controller IP, integrated PHY and MMAV™ for their high-performance ASIC chip. Siverge’s next-generation high-performance network processors allow for larger bandwidth and convergence of different protocols across networking systems and multiservice capabilities. Denali’s design IP, integrated PHY, and verification IP accelerates Siverge’s designers’ ability to design DDR2/3 memory systems, lower their integration risk, and speed their time-to-market for their new convergence chip.
“Denali Software, our IP vendor of choice, has provided us a high-quality configurable DDR2 IP solution, and helped us achieve our design and performance requirements which were critical to our time-to-market schedule,” said Uzi Zangi, vice president of Research and Development at Siverge Networks. “Our new convergence family of devices (code name Griffin) will support a large number of different interfaces, a huge number of different channels at various speeds and a uniquely wide range of protocols, thus meeting the needs of many key manufacturer and solution providers of all types of transport systems (wireline and wireless), switches and routers, multiservice switches and mobile RNC and BSC systems.”
The Databahn product provides a comprehensive infrastructure for configuring, analyzing, and generating the optimal memory controller for any given application. Denali’s Databahn combination DDR2/DDR3 memory controllers and Denali’s Databahn PHY products achieve speeds up to 1600 Mbps. Together, they offer a powerful, multi-port solution with configurable features and functionality to satisfy system performance requirements, significantly reducing integration and interoperability risks.
Siverge Networks’ Griffin (SV36xx) family of devices is Siverge’s flagship product family. Griffin family of devices re-defines the price, performance, power, functionality in the layer 1, layer 2 and layer 3 telecommunication market. Some members in Griffin family are unique ‘any port, any service, any system, and any network devices', targeted for next-generation transport systems as well switches and routers, multiservice switches, and Base Station Controller and Radio Network Controller systems. Other members are providing specific functionality and are introducing a refreshing cost reduction together with revolutionary integration level and without compromising feature. All of the Griffin family devices are package, pin, and software compatible enabling huge savings in research and development as well as inventory and maintenance: “one design, many (different) linecards and systems.”
“High-quality IP is essential to solving DDR2/3 memory system requirements, especially when dealing with sophisticated and high-throughput applications,” said Marc Greenberg, technical marketing director at Denali Software. “With our design IP products, which include support for the latest DDR2/3 specifications, we are providing customers with flexible memory systems, reducing their design risks, and enabling seamless integration into their system environment. We also realize the importance of providing a complete IP solution that helps to ensure that Siverge will be able to meet aggressive schedules for their designs and we are pleased to be working with Siverge to achieve this.”
About Databahn Solutions
Denali’s Databahn DDR-DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1/2/3, and LP-DDR1/2 devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification testbench, static timing analysis (STA) scripts, programmable register settings, and documentation. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/products/dram.
About MMAV
Denali's MMAV product is the industry's de-facto standard solution for modeling and simulating memory during functional verification. MMAV has been used in thousands of designs to ensure correct and optimal behavior and timing between the system design and off-chip memory devices. MMAV utilizes a powerful and effective approach to modeling memory. MMAV 2008 is available immediately. Additional MMAV 2008 information and an evaluation can be requested at: http://www.denali.com/mmav.
About Siverge Networks
Siverge Networks is a pioneering fabless semiconductor company at the forefront of networking technology. Siverge has developed unique core technology enabling OEMs to build low-cost high-speed packet based communication systems for fast expanding Carrier Networks. Siverge's patent-pending Packet Transport SoC re-defines the technology limits of networking devices by integrating 10x more functionality and channel/port count. Siverge devices enable exceptionally high capacity, true multi-service solutions and system consolidation for Fixed and Mobile Backhauling Networks. The company is headquartered in Herzelia (Israel) with an office in Orange County, CA (US). The company was founded in 2005 and is privately held. Website:
http://www.siverge.com/.
High-Quality Verification IP Provides Pre-silicon Compliance and Interoperability Verification and Faster TTM to Design Teams Beginning Early Gen 3 Development
SUNNYVALE, Calif., September 3, 2008 — Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced the availability of PureSpec™ PCI Express™ (PCIe) verification intellectual property (VIP) product which now supports the latest version of the Gen 3 specifications from the PCI-Special Interest Group (PCI-SIG®), allowing chip designers to begin early Gen 3 development. Denali’s PureSpec PCIe VIP product, a complete solution for modeling and verifying pre-silicon compliance and interoperability for PCIe designs, enables engineers to accelerate the design and verification of PCIe systems, and speed overall deployment of PCI Express technology.
“Having verification IP from Denali this early for the PCI Express 3.0 specification will give developers a chance to work with the latest in interconnect standards,” said John Wiedemeier, PCI Express Tools product marketing manager at LeCroy Corporation. “There is no doubt that companies, like Denali and LeCroy, will help enable the transition to PCI Express 3.0 technology with their industry-leading PCI Express solutions. Denali's PCI Express IP and LeCroy's protocol analysis tools reduce integration issues and speeds time-to-market.”
Denali's PureSpec verification IP software for the PCI Express protocol keeps pace with the PCI Express technology and specification as it continues to evolve. The upcoming PCIe 3.0 specification is the next evolution of PCIe technology and includes interconnect performance improvements, full compatibility with prior generations, and PCIe 1.x and 2.0 cards will seamlessly plug into PCIe 3.0-capable slots. All PCIe 3.0 cards will plug into PCIe 1.x and PCIe 2.0-capable slots. The PCIe 3.0 specification removes the requirement for 8b/10b encoding and uses it uses a 128/130 code and physical layer encapsulation.
“Our customers depend on high-quality verification IP solutions that are in step with the latest revisions from the PCI-SIG and we look forward to providing them the highest level of technology expertise,” states Sanjiv Kumar, director, Verification Products at Denali Software. “Our verification IP products not only support the next-generation protocol requirements for design and verification of PCI Express systems, but accelerate our customers’ design cycles and provide them with a clear roadmap for incorporating the latest specifications for their deployment of PCI Express technology.”
About PureSpec PCIe Verification IP
Denali’s PureSpec is the most widely used verification IP product for PCIe technology; over 250 PCIe designs have been validated using PureSpec verification IP. All PureSpec products are directly integrated into all popular EDA languages and verification environments including: Verilog, SystemVerilog, VHDL, C/C++, SystemC, 'e', OpenVERA. Quality, completeness and seamless integration with all modern verification environments, e.g., OVM, VMM, eRM, etc., make PureSpec the solution of choice for functional verification and interoperability validation of PCIe designs. For more information about PureSpec, visit: https://www.denali.com/purespec.
