FlashPoint Platform Supports ONFi 2.0 NAND Flash Technology for
PCIe-based Memory Systems

SUNNYVALE, Calif., July 31, 2008 — Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its Databahn™ memory controller IP and MMAV™ simulation models for design and verification, now include comprehensive support for Open NAND Flash Interface (ONFi) 2.0 device technology. Denali’s FlashPoint™ product, an end-to-end chip design platform for implementing memory sub-systems, also supports ONFi 2.0 device technology for PCI Express (PCIe) based Cache, and SSD applications.

“We are very pleased to announce support for the ONFi 2.0 device technology with memory controller designs and high-quality simulation models,” states Kevin Silver, vice president of Business Development at Denali Software. “Early availability of device models and memory controller products is consistent with our goal to speed the adoption of new memory technologies, and ultimately enable more efficient and high-performance memory subsystem design. The Flashpoint platform is a good example of how Denali’s taking this value proposition one step further by providing customers with a complete chip design, an end-to-end solution for PCIe-based flash memory systems, and as in this case, leverages all the features and functionality of ONFi 2.0 devices.”

“We are very pleased with the success of moving the ONFi 2.0 NAND Flash specification towards industry-wide support,” said Amber Huffman, Principal Engineer, Storage Technologies Group at Intel, and Technical Architect within the ONFi working group. “Enabling technologies, such as Denali’s commercial design and verification products, help to speed industry adoption of ONFi 2.0 devices in next-generation NAND Flash-based end applications.”

About MMAV 2008
Denali's MMAV product is the industry's de-facto standard solution for modeling and simulating memory for functional verification. MMAV has been used in thousands of designs to ensure correct and optimal behavior and timing between the system design and off-chip memory devices. MMAV utilizes a powerful and effective approach to modeling memory. MMAV 2008 support for ONFi 2.0 is available immediately. Additional MMAV 2008 information, including evaluation licenses, can be requested at: http://www.denali.com/mmav.

About Databahn Solutions
Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, and LP-DDR devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification test bench, static timing analysis (STA) scripts, programmable register settings, documentation, I/O pads and packaging. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/dram.

About FlashPoint
The FlashPoint platform is a complete system design, providing a PCI Express (PCIe) interface to high-performance NAND Flash memory. The platform uses a unique design configuration engine that enables the system to be tuned for optimal performance with differentiating features for a range of products, including PC cache modules, solid state drives (SSD), and ExpressCard™ devices. More information about the FlashPoint platform and its performance features can be accessed at: https://www.denali.com/flashpoint.

Industry-Leading Verification IP Solution Provides Full Specification Support of PCI-SIG IOV Technology Standard

SUNNYVALE, Calif., July 31, 2008 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its PureSpec™ PCI Express® (PCIe) verification intellectual property (VIP) product, supports the complete PCI-SIG® I/O Virtualization (IOV) specifications, now including Multi-Root IOV(MR-IOV). The PCI-SIG IOV suite of specifications minimizes system hardware and software requirements, allowing the simultaneous sharing of peripherals across multiple microprocessors and operating systems, increasing the performance of virtualized systems and enabling significant power savings. Denali’s PureSpec VIP allows verification engineers to verify their next-generation designs, ranging from server processors and network chipset to communication systems, for compliance to the latest PCIe standard, and take advantage of the newest set of IOV technologies.

“PCI-SIG recently announced its suite of specifications for I/O virtualization designed to improve performance and lower CPU/memory consumption,” states Al Yanes, PCI-SIG President. “PCI-SIG values Denali’s contributions to the industry adoption of our specifications through its work to develop IP products that support the suite of PCI-SIG IOV standards.”

“Denali understands the challenges facing design teams, including the complex IOV requirements for complex server, switch and router systems,” states Sanjiv Kumar, director of VIP products at Denali Software. “As a provider of PCIe verification IP, our customers use our complete high-quality verification IP that addresses all aspects of the latest PCI-SIG specification. Their designs can meet PCI-SIG IOV compliance and help verification engineers significantly shorten their validation cycle.”

About Denali PureSpec
Denali's PureSpec verification IP software for PCIe is the most widely used solution for verifying functionality, compliance and interoperability of PCIe designs at the pre-silicon stage of chip or IP core development. PureSpec supports the latest PCI-SIG specifications for Address Translation Service, Single-Root and Multi-Root I/OV, including configuration spaces (physical function, virtual function and base function), Alternative Routing-ID interpretation, Functional Level Reset (FLR), and PCI Manager (PCIM) capabilities. For more info about PureSpec and its benefits in your next design, visit https://www.denali.com/vip.

Expanded Working Group to Deliver Next Version of DDR PHY Specification Minimizing Design and Integration Cost Benefits with Reusable IP

SUNNYVALE, Calif., July 23, 2008 – Denali Software, Inc., today, as one of the DDR PHY Interface (DFI) specification participating members including ARM, Denali, Intel, and Samsung, announced that LSI Corporation and STMicroelectronics have joined the collaborative technical working group for the industry standard DDR-PHY Interface (DFI) specification, which simplifies the interoperability between the memory controller and PHY. Representatives from these industry-leading companies make up the collaborative technical working group, which plan to contribute to improvements and enhancements in the next version of the DFI specification. With the expanded technical working group, including LSI and STMicroelectronics, the ongoing development of the specification will continue to benefit PHY providers, chip architects and memory controller vendors, speeding their DDR memory system design and integration, reducing significant verification costs.

“Industry-accepted interface specifications simplify development and facilitate interoperability,” said Don Friedberg, director of Foundation IP Solutions at LSI Corporation. “The DDR-PHY Interface specification will help streamline the integration of memory interface PHYs with high-performance controllers.”

“STMicroelectronics is a strong promoter of open industry standards. Parallel DRAM interfaces are increasingly becoming a performance driver for many of our system-on-chip products in computer peripheral, consumer, telecom, and wireless applications,” said Pierre Dautriche, AMS and PHY IPs director at STMicroelectronics. “It is therefore natural that ST joins the DFI standardization body, which will benefit our customers with higher performance in our DDR interfaces.”

This current version of the specification, DFI 2.0, available through a click-thru license at: www.ddr-phy.org, supports DDR1, DDR2, Mobile, and DDR3 memory; adds read, write, and gate training interfaces; and improves upon the interoperability features between the memory controller and a DDR PHY. The official version of the specification has been based on the 1.0 foundation of the common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs. This specification allows designers a standard that has wide industry acceptance and ensures that the controller and PHY will work optimally together and no changes will be required to the hardened logic, resulting in reduced cost, time-to-market, and increasing reusable system IP. Further DDR DRAM and PHY technical discussions, presentations, and supporting technologies will be highlighted during the upcoming MemCon event, “The Technology Roadmap for Memory and Storage,” in Santa Clara, CA., from July 21-24.

“LSI and STMicroelectronics coming aboard as technical contributors to the next DFI specification represent the significant awareness and the importance of a standard interface between the controller and PHY,” said Bryan Jones, who oversees Corporate External IP Management for Intel’s Mobility Group. “Amidst the growing community of technology experts and interface users, the contributions from the expanded technical team will increase further industry adoption, technical advancement, and exciting opportunities.”

“With these new additions to the contributing technical committee, we look forward to improvements in the next version of the existing specification,” said Brian Gardner, vice president of IP products at Denali. “The industry will continue to benefit from memory controllers and PHYs that fall in line with the specification, providing enhanced interoperability and high performance.”

About the DFI Specification
The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, visit: www.ddr-phy.org.

PCI Express is a registered trademark of PCI-SIG.

First Provider of Memory Controller and PHY Solution to Support LPDDR2 in Next-Generation Mobile and Embedded Applications

SUNNYVALE, Calif., July 21, 2008 — Denali, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its Databahn™ memory controller and PHY IP supports the pre-released LPDDR2 specification, as currently defined by JEDEC - the leading developer of standards for the solid-state industry. Chip designers and system architects desiring to upgrade to LPDDR2 can learn more about Denali’s new upcoming LPDDR2 offering, which will include both varieties of SDRAM (S2/S4) in the memory controller and PHY IP and support for Non-Volatile Memory (NVM) by attending the MemCon presentation, “Next-Generation Low-Power LPDDR2 Memories: How to Use Them in Your Mobile and Embedded Designs” at 1:30pm on Wednesday, July 23 in Santa Clara, CA. Denali’s Databahn LPDDR2 memory controller and PHY will be well suited for low power and embedded system designs which target applications as cell phones, ultra-mobile PCs, and consumer applications, addressing design requirements of density, speed, and power.

“We are pleased to see member companies introduce next-generation technologies that fully support the LPDDR2 industry specification. It is this type of advanced industry adoption that helps to establish high quality and reliability benchmarks required for low power and embedded system memory design,” said Roger Isaac, chair for the JEDEC JC-42.6 Low Power Memory Committee. “Denali is an active committee participant, working closely with memory vendors like Spansion to provide valuable recommendations toward the development of the specification.”

Denali’s LPDDR2 memory controller and PHY will support the full specification when released by JEDEC. LPDDR2 addresses the needs of mobile and consumer systems where the “PC memory” devices, DDR2 and DDR3, are unsuitable, as LPDDR2 offers a low power, low voltage, low pin-count memory in a range of densities and speeds that are closely matched to the needs of those mobile and consumer systems. In addition, LPDDR2 was designed to allow sharing of SDRAM and NVM memory on the same bus, which is extremely difficult in PC memory technologies. For immediate availability of a C-model, in advance of the silicon IP for Denali’s Databahn LPDDR2 memory controller and PHY, contact sales@denali.com.

“Many of our customers are looking for ways to upgrade to new controller technologies and are faced with several challenges,” states Marc Greenberg, director of Technical Marketing for Databahn products at Denali Software. “Many of the LPDDR2 features are derived from the best features of the LPDDR1, DDR2 and DDR3 technologies that we already support. This gives Denali an accelerated position to support the LPDDR2 architecture and continue to provide our customers with high-quality, interoperable, and configurable IP solutions.”

About Databahn Solutions
Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, and LP-DDR devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification test bench, static timing analysis (STA) scripts, programmable register settings, documentation, I/O pads and packaging. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/dram.