Sole Provider of Memory Controller and Hard PHY Solution to Support Both DDR3 Chips and Modules for Networking, Storage, and Personal Computing

SUNNYVALE, Calif., May 29, 2008 — Denali, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced the immediate availability of its Databahn™ DRAM memory controller and hard PHY IP with full DDR3 dual in-line memory module (DIMM) support designed for bulk-memory and caching applications, including networking, storage and personal computing. Denali announced embedded systems support for discrete DDR3 DRAM chips last year as memory vendors began offering new devices to support data rates up to 1600Mbit/s per pin. This new DDR3 DIMM offering adds unique capabilities in the memory controller and PHY IP that are needed for networking, storage and personal computing systems using DDR3 modules at data rates up to 12.8GBytes/s per DIMM.

“The DDR3 DIMM is a high-volume product used by SoC customers who require a large amount of high-bandwidth memory,” remarked Brian Gardner, vice president of IP products at Denali Software. “To achieve this higher bandwidth, DDR3 DIMMs utilize a “fly-by” architecture which requires read and write leveling and gate training capabilities to be directly implemented and managed in both the DRAM controller and the PHY. Our customers look to Denali to provide high-quality, interoperable, and configurable IP that supports the DDR3 DRAM architecture where DIMM concepts can be applied.”

About Databahn Solutions

Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, and LP-DDR devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification test bench, static timing analysis (STA) scripts, programmable register settings, documentation, I/O pads and packaging. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/dram.

New Models for Latest Memory Technologies Plus Advanced Features and Support for Standard Protocols Increases Productivity and Minimizes Design Risks

SUNNYVALE, Calif., May 22, 2008 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced the availability of the new MMAV 2008 packaging, the most widely-used memory verification IP product. Denali's MMAV has become an industry-standard solution for verifying memory interfaces and ensuring system correctness. This latest package release provides a complete and an accurate solution for simulating memories, including support for most of the memory technologies, including DRAM, SRAM, Flash, and Card memories, and several standard protocols. Verification engineers can utilize MMAV memory verification IP early on in their design cycles, minimizing the risks of non-compliance and ensuring chip success.

"Denali continues to strive to deliver the highest-quality of simulation models for cutting-edge memory technologies," remarks Sanjiv Kumar, manager, Verification Products at Denali Software. "Our tens of thousands of pre-verified memory models support various parts from all major memory vendors and deliver the best quality and reliability needed for our customers' system memory requirements. The advanced MMAV architecture allows seamless integration with different verification methodologies like eRM, VMM, OVM, etc."

MMAV 2008 can be utilized for cutting-edge memory technologies and provides new simulation models for mobile DDR (LPDDR), mobile DDR2, ONFi, GDDR4/5, eSD, eMMC and also for SystemRDL, DFI, AMBA (AXI, APB, AHB), and OCP protocols. Additional new advanced features found in MMAV 2008 includes transaction callback, assertions report generation, and error configurability. PureView, a supporting MMAV product, incorporates Blueprint Compiler technology, which generates necessary outputs and views for design, verification, documentation, software development, post silicon debug and even enables early software development with SystemC™ Transaction Level models. For an overview on MMAV 2008 and its new advanced verification techniques, stop by to speak to our experts at the Denali booth (#1611) at the Design Automation Conference (DAC) in Anaheim, CA., during June 9-12, or register now for an in-depth presentation and hands-on tutorial, "Increase Your Productivity with High Quality Memory Verification IP," at MemCon San Jose, on Monday, July 21, 2008.

About MMAV

Denali's MMAV product is the industry's de-facto standard solution for modeling and simulating memory during functional verification. MMAV has been used in thousands of designs to ensure correct and optimal behavior and timing between the system design and off-chip memory devices. MMAV utilizes a powerful and effective approach to modeling memory. MMAV 2008 is available immediately. Additional MMAV 2008 information and an evaluation can be requested at: http://www.denali.com/mmav.

Widely-Used DDR Memory System Specification Takes Advantage of DDR3 Performance and Minimizes Design and Integration Costs

SUNNYVALE, Calif., May 21, 2008 – Denali Software, Inc., today, as one of the DDR PHY Interface (DFI) specification participating members including ARM, Denali, Intel, and Samsung, announced the release of the new DFI specification version 2.0. The collaborative technical working group, which includes representatives from these companies, delivered several improvements and enhancements in this latest version of the DFI specification. This version of the specification extends support to include DDR1, DDR2, Mobile, and DDR3 memory; adds read, write, and gate training interfaces; and improves upon the interoperability features between the memory controller and a DDR PHY. Chip architects, memory controller vendors, and PHY providers can utilize the new specification to speed their DDR memory system design and integration, and reduces the significant verification costs.

“DDR3 created some technical challenges for this industry collaboration. The team rose to the task, and the result is a specification that ensures interoperability and high performance,” said Brian Gardner, vice president of IP products at Denali.

The DFI specification 2.0 is available through a click-thru license at: www.ddr-phy.org. The official version of the specification has been based on the 1.0 foundation of the common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs. This specification allows designers a standard that has wide industry acceptance and ensures that the controller and PHY will work optimally together and no changes will be required to the hardened logic, resulting in reduced cost, time-to-market, and increasing reusable system IP.

“As many designers are migrating from DDR2 to DDR3 technologies to take advantage of the performance, this places a massive load on the controllers and increases the importance of a standard interface between the controller and PHY,” said Bryan Jones, Corporate External IP Management, Mobility Group for Intel Corporation. “The contributions from the technical team help to increase momentum and opportunities, and we look forward to furthering the usage of this specification within the industry.”

About the DFI Specification
The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, visit: www.ddr-phy.org.