New ESL Methodology Incorporates CSR Automation Management for Hardware and Software Design Accelerating Development Process

SUNNYVALE, Calif., March 27, 2008 —Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced it has licensed its Blueprint™ product to Atheros Communications, Inc., a leading developer of advanced wireless and wired solutions. Atheros will employ Blueprint's SoC design tools in developing the company's Radio-on-Chip for Mobile® (ROCm®) solutions and other products. The Denali Blueprint Compiler was specifically designed for hardware and software engineers to generate and manage all control registers throughout the design process, to speed pre-silicon validation, maintain architectural quality and thus, increase productivity.

"The Blueprint system-level design tool significantly reduces integration time, helps ensure consistency and eases propagation of changes throughout the design and verification process," said Steve Padnos, methodology architect for Atheros. "Atheros selected Denali because it provides an integral and valuable platform solution for SoC design."

"Denali understands the challenges facing design teams and the error-prone processes that occur between the register specification and implementation prior to finalizing the design requirements," said Mark Gogolewski, CTO at Denali Software. "Our customers, such as Atheros, can utilize Blueprint Compiler to significantly shorten the time required to pre-silicon hardware/software integration and build complex SoCs."

About Denali Blueprint

Denali Blueprint is a SystemRDL compiler that enables a system-level approach to automating specification, view generation, and management of control registers for IP and SoC design. Blueprint will generate necessary outputs and views for design, verification, documentation, software development, post silicon debug and even enables early software development with SystemC™ Transaction Level Models. Blueprint guarantees interoperability with other EDA tools by inputting and outputting IP-XACT and SystemRDL formats. For more information about Blueprint, visit:
blueprint.

For more information, contact:

Editorial Contact:
Pierre Golde
Denali Software Inc.
650.461.7262
pgolde@denali.com

--end--

Denali's Comprehensive DDR2/3 DRAM, Hardened PHY, and PCI Express Products Enable Netronome to Maximize Performance in Next-Generation Network Flow Processors

SUNNYVALE, Calif., March 05, 2008 —Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Netronome Systems, Inc., has selected Denali's Databahn™ DDR memory controller IP, integrated DDR hard PHY, and PCI Express (PCIe) controller IP for their high-performance network processors. Netronome's next-generation high-end network flow processors enable manufacturers to accelerate application level processing in several Layer 2-7 markets including switching and routing, network security, broadband access, test and measurement and wireless markets. Denali's design controller IPs accelerate Netronome's designers' ability to design in DDR2/3 and PCIe, lower their integration risk, and speed their time-to-market for delivering their network processors in silicon.

"Working with a leading IP provider, such as Denali Software, who provides a comprehensive tailored data solution and verification environment, will helps us achieve our time-to-market goals in a cost-effective way," said Jim Finnegan, senior vice president of Engineering at Netronome Systems, Inc. "Our performance and configurability requirements were achievable with Denali's flexible DFI-compliant DDR2/3 controller, DDR2/3 PHY and PCIe 2.0 solutions. These subsystem components are important ingredients in our high-performance 65-nm Flow processor which provides unsurpassed L2-L7 processing capability for our customers."

The Databahn portfolio provides a comprehensive infrastructure for configuring, analyzing, and generating optimal controllers for any given application interface. The Databahn combination DDR3/DDR2 memory controllers and hardened PHY products achieve speeds up to 1600 Mbps. Together they offer a powerful, multi-port solution with configurable features and functionality to satisfy system performance requirements, significantly reducing integration and interoperability risks.

The Network Flow Processor (NFP) family is highly flexible and programmable with a high-performance parallel processing architecture for processing complex Layer 2-7 algorithms, deep packet inspection, encryption, PKI hardware acceleration, traffic management and forwarding at wire speed. The NFP multi-core architecture combines 40 multi-threaded microengines, each with 8 threads per microengine, optimized for packet processing.

"High-quality IP is essential to solving DDR2/3 memory system requirements and for incorporating PCIe 2.0 technology, especially when dealing with sophisticated and high-throughput applications," said Brian Gardner, vice president of IP products for Denali. "With our design IP products, which include support for the latest DDR2/3 and PCIe 2.0 specifications, we are providing customers with flexible, high-performance controller IP, reducing their design risks, and enabling seamless integration into their system environment. We also realize the importance of providing a complete IP solution that helps to ensure that Netronome will be able to meet aggressive schedules for their designs and we are pleased to be working with Netronome to achieve this."

About Databahn Solutions

Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, GDDR3, GDDR4, GDDR5 and LP-DDR1/2 devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification testbench, static timing analysis (STA) scripts, programmable register settings, and documentation. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit:
http://www.denali.com/dram/.

Denali's Databahn PCI Express is a high-quality design IP product that reduces risk and speeds time-to-market for deploying PCI Express interfaces in silicon. The Databahn PCIe core has been implemented in production silicon and successfully deployed in several leading OEM server products as well as extensively tested with all major chipsets and motherboards. The Databahn PCIe core supports the latest PCI-SIG 2.0 specifications and has many customer tape outs. Find out more about Databahn PCIe solutions at: http://www.denali.com/pcie/.

About Netronome Systems

Netronome Systems develops high-performance network flow processing, deep packet inspection and application acceleration solutions for networking, communications and security appliance manufacturers and the IT organizations that use them. Headquartered in Pittsburgh, Pennsylvania, with North American offices in Santa Clara, California and Boston, Massachusetts, Netronome has international operations in Centurion, South Africa; Cambridge, United Kingdom; Shenzhen and Hong Kong, China; and Penang, Malaysia. To learn more about the company and its products, please visit www.netronome.com or call +1 877 NETRO A-Z (+1 877 638 7629).

About Denali Software

For more information, contact:

Editorial Contact:
Pierre Golde
Denali Software Inc.
650.461.7262
pgolde@denali.com

--end--