PALO ALTO, Calif., February 06, 2008 — Denali Software, Inc., today, on behalf of all DDR PHY Interface (DFI) specification participating members, including representatives from industry-leading companies ARM, Denali, Intel, and Samsung, announced the release of the latest DFI specification version 2.0. The growing community of technology experts and interface users are invited to comment and provide feedback to the specification before its formal release within the next 30 days. System developers, memory controller vendors, and PHY providers can benefit from the increased interoperability and use of new DDR3 features such as read and write leveling, thereby accelerating DDR memory system deployment and reducing the significant integration and verification costs. This enhanced version of the DFI specification will be highlighted this week in the Denali booth (#322) at DesignCon in Santa Clara, CA.

"With the rapid adoption and benefits realized from the initial DFI specification, the DFI working group has been concentrating their efforts on improving the specification for increased integration and verification between the PHY and memory controllers," said Bryan Jones, IP outsourcing program manager, Mobility Group, Intel Corporation. "The additional inputs from the community will improve the existing expanded specification and significantly minimize the design and integration cost benefits attributed to the reusable IP in this space."

Since last year's International Engineering Consortium DesignVision award for the 1.0 specification, over 1000 engineers from over 500 companies have downloaded the specification. The DFI specification 2.0, built on the 1.0 foundation of the common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs, allows designers a standard that has wide industry acceptance and be confident that the controller and PHY will work optimally together and no changes will be required to the hardened logic, resulting in reduced cost, time-to-market, and increasing the reuse of the individual components that make up the memory system. Submit all comments to the DFI 2.0 specification by March 5 at: www.ddr-phy.org.

"We realize the need to evolve the specification and gather the best technical contributions from around the world," said Brian Gardner, vice president of IP products at Denali. "With such a large and diverse community behind this initiative, it represents the best example of a successful standardization process; one where users, vendors, and even competitors work together toward a shared goal."

About the DFI Specification

The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, visit: www.ddr-phy.org.

For more information, contact:

Editorial Contact:
Pierre Golde
Denali Software Inc.
650.461.7262
pgolde@denali.com

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Maynard, MA and PALO ALTO, Calif., February 05, 2008 — Signal Integrity Software, Inc. (SiSoft™) and Denali™ Software, Inc., today announced they will co-present "Counting the Picoseconds: Integrating Timing, Signal, and Power Integrity Analysis", on Wednesday, February 6, from 2:00PM to 2:40PM at DesignCon 2008 in Santa Clara, CA. This joint presentation focuses on a key challenge in today's high-speed design industry – the challenge of modeling the effects of timing, power and signal integrity in a truly integrated fashion.

"Increasing design speeds have driven operating margins down into the tens of picoseconds range," stated Barry Katz, president and CTO of SiSoft. "Combined power/signal integrity analysis is no longer an option – it's crucial to success."

"Customers today demand a total solution for DDR memory subsystems, from memory market research to memory controller tuning to a flexible hard PHY to designing and validating IO, package and board designs," stated Brian Gardner, Denali's vice president of IP products. "We are pleased to be working with SiSoft, an industry leader in signal integrity design."

"Only SiSoft's Quantum-SI™ toolset provides the capability to simultaneously evaluate package and PCB effects with respect to power integrity, crosstalk, topology, termination, and IO drivers, and produce concise signal quality and timing margin reports," said Barry Katz.

Additionally, SiSoft and Denali experts will both be demonstrating Quantum-SI DDR3 kits with Denali controllers, during the exhibition on the show floor (booth #106 and booth #322). Exhibition hours are from 12:30PM to 6:30PM on both Tuesday and Wednesday, February 5-6. If you are unable to attend DesignCon 2008 and would like additional information, contact via email at: rkatz@sisoft.com or phone (978) 461-0449, x15.

About SiSoft™

SiSoft™ is the leading provider of integrated timing and signal integrity solutions for high-speed digital system design. SiSoft's Quantum-SI™ products allow users to rapidly determine interface operating margins and achieve High-Speed Timing Closure, providing unprecedented accuracy in predicting system-level noise and timing margins. Quantum-SI Interface Analysis Kits are pre-configured analysis setups for popular interface standards that encapsulate both interface architectures and design requirements to accelerate the high-speed design process.

SiSoft ensures its tools remain at the forefront of high-speed design by providing advanced high-speed consulting services including model development, I/O characterization, package design/analysis and system-level interconnect analysis. SiSoft design consultants utilize SiSoft's own commercial software to address some of the industry's most demanding design problems, helping ensure software product quality and enhancements while driving future development. More information on SiSoft, its products and services can be found at www.sisoft.com.

TRADEMARKS

SiSoft, Quantum-SI, Quantum Channel Designer, Core-to-Core, TransferNet, High-Speed Timing Closure and High-Speed Design Closure are trademarks of Signal Integrity Software, Inc.

For more information, contact:

Editorial Contact:
Ronda Ivey Katz
Sr. Mktg. Comm. Mgr.
SiSoft
(978) 461-0449, x15
rkatz@sisoft.com

Editorial Contact:
Pierre Golde
Denali Software Inc.
650.461.7262
pgolde@denali.com

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