Newly introduced and available for pre-availability orders, the privately branded 2.5-inch SSDs from established Apple Mac component vendor OWC (Other World Computing) are a sign of the rapidly changing SSD landscape with respect to mass marketing of solid-state drives to end users. The Mercury Extreme Pro series of SSDs range in capacity from 50 to 480 Gbytes and they physically look pretty much like every other SSD out there (milled, blue-anodized aluminum cases notwithstanding). These drives are based on SandForce’s SF-1500 SF-1200 controller chip and what’s significant about the introduction of these drives is that OWC is passing through a significant chunk of SandForce’s technology and terminology but reframing that information and passing some if it along at a less technical level. In other words, OWC has substantially transformed SandForce’s tech speak features through words and pictures into important benefits easily understood by end users. This mass marketing approach opens a new front in the SSD wars.

First, OWC offers two versions of the Mercury Extreme Pro SSD. There’s an RE version (RE stands for RAID-ready enhanced) and a non-RE version. The RE versions have capacities of 50 to 400 Gbytes and cost $230 to $1600. The non-RE versions have capacities of 60 to 480 Gbytes and cost $220 to $1580. OWC’s marketing materials make it very clear that the difference between these drives is SSD controller firmware and that the RAID enhancements are based on SandForce’s RAISE (redundant array of independent silicon elements) technology. RAISE, one component of SandForce’s so-called DuraClass technology, distributes data across the various NAND Flash chips within the SSD using RAID-like algorithms. SandForce claims that this technique coupled with extended ECC algorithms reduces the chance of read errors by 100x. OWC highlights quotes from the SF-1500 data sheet to bring the complexity level of the claim down a notch or three and to push a benefit that’s easily understood by client-level users:

“Best in class error correction (ECC) and SandForce RAISE™ (Redundant Array of Independent Silicon Elements) technology provides RAID like data protection and reliability without loss of transfer speed due to parity.”

Another fascinating facet of the differentiation between the RE and non-RE versions of OWC’s Mercury Extreme Pro is the explicit discussion of capacity overprovisioning. The non-RE SSDs are 7% overprovisioned and the RE versions are 28% overprovisioned, which partially helps to explain the difference in drive capacities and the different warranty periods (3 years for the non-RE drives versus 5 years for the RE drives).

However, the convincer for most client-level SSD buyers isn’t going to be all the text claims. It’s more likely to be the marketing graph OWC has posted that shows how the write speed of Mercury Extreme Pro SSDs doesn’t degrade over time as do unnamed “competitive” SSDs. Here’s the graph:

Who in their right mind would pick an SSD that rapidly approaches a zero Mbytes/sec write throughput as shown in the graph above? No one, that’s who. Yet this is clearly a “marketing” graph, lacking numeric scales for both the X and Y axes. Even without numbers however, you have to admit that the graph does its job.

OWC has also posted a boot video similar to the one we blogged earlier (See “Corsair Video vividly shows SSD speedup on laptop”) but for a MacBook Pro booting up with SSD assistance instead of a PC. Videos like these from Corsair and OWC make it tangibly clear why an end user would want in SSD in their laptop of PC. They're selling the sizzle, not speeds and feeds.

These ongoing changes in the way SSDs are marketed point toward the beginning of a maturation in the SSD market. As SSD prices continue to fall and as capacities continue to rise, SSDs become increasingly attractive to a larger number of end users, and changes in the way SSDs are marketed to these prospects reflect that evolution.

From North Carolina State University (NCSU) comes news of a materials breakthrough that promises extreme density for magnetic RAM (MRAM) devices, possibly in as little as five years or so. Dr. Jay Narayan, the John C. Fan Distinguished Chair Professor of Materials Science and Engineering at NCSU, presented a paper last month at the spring meeting of the Materials Research Society (MRS) detailing his team’s success in patterning high-density, magnetic nanodots on a silicon substrate using self-assembly processing of nanodots made from magnetic materials such as Ni, Ni-Pt, Fe-Pt during thin film growth by pulsed laser deposition. Each nanodot is a single, defect-free crystal that could be used for bit storage on a silicon chip. From the many news stories on the Web, it appears that the current processing technology has produced 10nm nanodots, capable of storing about a Tbit (terabit) per square cm but Narayan says that the technology could be pushed to 6nm nanodots.

Let’s be clear about the announcement, because many of the existing online reports of this development (like this one on Slashdot) are somewhat fuzzy as to just what Dr. Narayan’s team has accomplished: they’ve developed a process to deposit a regular array of magnetic nanodots on a silicon substrate. They have not developed a “chip” because there is no circuitry on that silicon—so far—to address, write, or read the nanodots and therefore these wafers are not yet functional storage devices as portrayed by the headlines of several stories covering this development. Consequently, Dr. Narayan’s time horizon of five years to usable devices seems about right. Conventional CMOS processing hasn’t quite caught up to the 10nm nanodot geometries, much less the extrapolated 6nm. For example, Xilinx is only talking about shipping 28nm logic devices next year and current memory devices are shipping with geometries in the 30-50nm range. Consequently, there are many things that still need to come together to make Dr. Narayan’s magnetic nanodot into a viable storage element. As Dr. Narayan wrote back in an email, “The rest is to follow.”

Hot on the heels of Numonyx’ announcement of two commercial PCM (phase-change memory) products (see “Numonyx 128-Mbit serial- and parallel-I/O PCM non-volatile memories now available in volume”), Samsung announced on April 28 that it plans to ship a device “later this quarter” that integrates DRAM and PCM devices into a multichip package (MCP). Samsung has named its flavor of PCM “PRAM” for “Phase-change RAM.” The PRAM in this MCP is a 512-Mbit device and its intended use is for replacing the NOR Flash memory that currently stores code for a Smartphone. Samsung claims that the PCM used in this new device is three times faster than the NOR Flash it replaces.

Perhaps just as important, both the PCM and DRAM chips in the announced MCP employ the LPDDR2 interface. Consequently the MCP need only present one LPDDR2 interface and one set of pins to the outside world, while distributing the LPDDR2 signals to the two chips internally. In addition, the Smartphone SOC or ASSP only needs one LPDDR2 interface and one set of interface pins to connect to the announced device. These pin efficiencies are no doubt possible because of the LPDDR2-NVM interface extensions specifically created to allow non-volatile memory to easily coexist with LPDDR2 memories (see “State-of-the-Art in Low-Power Memory: Denali’s MemCon”). Although the LPDDR2-NVM spec was developed for Flash devices, it appears to work just as well for PCM devices.

Note that Samsung’s announcement differs from the Numonyx announcement of commercial devices in one significant way. Numonyx announced the immediate availability of its two PCM devices in production volume and included the immediate availability of downloadable, detailed data sheets. Samsung’s announcement is of the imminent shipment of a PCM-based device.

Sometimes it takes decades but NAND Flash semiconductor memory is turning out to be quite the media killer. Over the last decade, NAND Flash memory has killed off 35mm photographic film for all but the most dedicated still-photography enthusiasts. With the advent of dSLR (digital single-lens reflex) cameras that also shoot video, such as the Canon 5D and 7D dSLRs, NAND Flash memory now seriously threatens to replace photographic film for movie and TV production because of the lower costs and faster workflows. The latest confirmation of NAND Flash’s lethal effects is this announcement in the Washington Post reporting that Sony plans to terminate production of floppy disks and will stop selling them in Japan next year after producing them for 30 years. For many who thought the floppy disk dead already, it may come as a surprise that they are still in production but they are apparently still in use in Japan where Sony claims to own more than 70% of the market. NAND Flash simply offers computer users many advantages including more capacity, better performance, and more ruggedness compared to the venerable floppy. Soon, the only remnant of the floppy disk’s former glory may well be the icon on a Microsoft Office application toolbar that serves as a shortcut for saving a document or file.

The proven lethal effects of NAND Flash on other portable media also point to the current controversy between SSD and HDD advocates. Hard disk drives retain their lead over SSDs in storage capacity and storage cost/bit and HDD vendors continue to move heaven and earth to maintain that lead. SSD vendors seem just as eager and determined to overtake HDD vendors and the historic record of NAND-Flash-based storage devices’ ability to kill older, competing media formats is pretty compelling. Already, enterprise-class storage systems are finding compelling applications for SSDs as storage accelerators. Leading-edge PC users including gamers and video producers find SSDs compelling for their speed, albeit at a higher cost for storage. Today, SSDs are mostly used as HDD helpers. Tomorrow may be another story. It obviously won’t happen next year or even the year after that, but I wouldn’t bet against the ultimate outcome.

Wondering whether an SSD really makes that much difference to laptop performance? Wonder no longer. Corsair has posted the following video that graphically illustrates how much faster boot and application loading times are when there’s an SSD present. This video should leave no doubt in your mind. In particular, watch as the video has to speed up while the HDD-equipped laptop is doing pretty much nothing.

Numonyx has announced or reannounced two 128-Mbit non-volatilve memory devices based on the company’s 90nm PCM (phase change memory) process technology. These two devices target existing NOR Flash memory sockets and the company’s press release claims that both products are available now in production quantities. The two announced PCM memory devices are the Omneo P8P PCM parallel-I/O memory and the Omneo P5Q PCM serial-I/O memory. The Omneo P5Q PCM device is configured as a 16Mx8-bit memory and employs an SPI interface and supports dual and quad SPI protocols. The Omneo P8P PCM device is configured as an 8Mx16-bit memory with a 16-bit parallel I/O interface and the device has a secondary SPI channel for issuing block commands to the device and for low-pin-count, in-system programming.

The initial read access time for the parallel PCM device is given as 115 nsec with 25 nsec for subsequent reads during 8-word (the parallel device is configured as a x16-bit memory) , asynchronous page reads. Write cycle time is a short 70 nsec, but the writes are buffered internally by a 64-byte FIFO that masks the actual cell-specific write time. Using the same memory cell, the serial P5Q PCM memory device’s read-access time is constrained by the SPI interface, not the fundamental access time of the memory cell. One of the big advantages of PCM over NOR Flash is the ability to directly write one memory location with no need for an erase cycle.

Two significant attributes of the devices, made significant because of the technical issues surrounding, are the announced write endurance and the operating temperature range of the devices. Numonyx had previously announced a version of the P8P PCM with 100,000-cycle write endurance. The latest announcement jumps the rated write-cycle endurance for both the P8P and the P5Q memory devices to 1M write cycles.

Operating temperature is important because PCM employs a thermally activated storage mechanism. Ones and zeroes are stored in PCM cells based on a heating/cooling cycle. Fast cooling produces an amorphous state in the PCM’s chalcogenide material and slow cooling essentially anneals the cell into a crystalline state. If the ambient temperature is too high, the heat alone will start to anneal PCM cells. Numonyx’ data sheets give both memories’ operating temperature range as 0 to 70° C.

With data sheets on line and announced volume availability, these two PCM devices from Numonyx appear to the first commercially available, commercially viable PCM devices on the market. Numonyx is not currently disclosing pricing except to say they’re currently charging a premium given that the devices are not very far down the learning curve. However, given the activity that the company has put into presentations and articles over the past two years, they likely are not the last.

One of the most ignored Intel announcements of recent memory must be Doug Davis’ early disclosure at IDF (China) on April 14 (see the hour-long keynote video here) of the company’s new Atom-based Tunnel Creek, an SOC specifically designed for embedded applications. Intel’s Atom processor, a relatively low-powered implementation of the “Intel Architecture,” has been taking the low-end notebook and netbook world by storm. Atom processors also work well and have been rapidly adopted in the embedded world when the embedded product’s block-diagram resembles a PC. However, smaller embedded systems can’t adopt the multichip, chipset-style design of PCs. Many smaller embedded systems require even fewer chips for cost-effective implementation.

Enter Intel’s Tunnel Creek, which sports four x1 lanes of PCIe in addition to the Atom processor core; memory, audio, and video controllers; and an LPC block. The simple addition of a flexible PCIe interface means that embedded designers can gluelessly add a variety of different chips to the Tunnel Creek SOC to create embedded designs with minimal BOMs.

Figure 1: Intel Tunnel Creek block diagram

What can you connect to a PCIe interface that would be useful in an embedded design? Here are just a few ideas that immediately come to mind:

1. An ASSP with a PCIe interface. In the same talk where he disclosed Tunnel Creek, Davis also mentioned that Intel will be developing more than one application-specific I/O hub for specific use with Tunnel Creek. In addition, there are many other likely candidates already on the market such as advanced video/graphics controllers from companies such as nVidia and fast Ethernet controllers from companies such as Realtek.
2. An FPGA. Both Xilinx and Altera offer FPGAs with integral PCIe interfaces. Imagine the ability to gluelessly graft an FPGA directly to an Intel Atom-based SOC. Tunnel Creek should be able to do that.
3. An SSD. You can get PCIe-based SSDs that provide more performance than SATA- or SAS-interfaced SSDs because the PCIe interface is more efficient for high-speed I/O than disk-centric interface protocols. Why add an unneeded disk controller to the mix?
4. Your own ASIC. Intel and TSMC announced earlier that the Atom core would be available to select customers as an ASIC/SOC core. Perhaps you don’t have the production volumes needed to qualify as a select customer for that program but you’d still like to avail yourself of Intel’s processor architecture because of the immense pool of existing software, the many available operating systems for the x86 architecture, and the broad development tool support. Tunnel Creek gives you a way of doing so using a standard processor-based SOC that will likely be produced in fairly high volumes. For lower production volumes, a 2-chip embedded design may well be the most economical.

If these possibilities excite your inner design muse, then start bothering Intel to see when you can get your hands on some Tunnel Creek samples.

Network World has just posted an SSD comparison test written by Logan G. Harbaugh. The test pitted some consumer-class SSDs against enterprise-class SSDs and with an Adaptec ASR5805/512 SSD controller and MaxIQ kit, which uses an attached SSD to accelerate attached drives arrays via flash caching. Overall, Harbaugh found that the SSDs improved system performance by a factor of 2 to 10 depending on the product.

The discussed test results illustrate many key points we’re learning about SSDS used both as direct storage devices and as caches for rotating storage. For example, the article discusses the “write cliff,” which is the sudden loss of write performance sustained by some SSDs after they are initially filled. The cause of the performance loss is the need to scavenge free space from deleted files and the need for “wear leveling,” which prevents premature NAND Flash failure in the SSD. If the SSD capacity is not overprovisioned (larger than the rated size), then writes cannot progress until the SSD’s controller finds, liberates, and organizes the free space. If the SSD capacity is overprovisioned, then free-space “garbage collection” and wear leveling can occur as a background task and will not increase the drive’s write latency. The write latency of an SSD that’s not overprovisioned can range unpredictably from milliseconds to seconds depending on the amount of free space to be liberated. Of course, there’s a cost for capacity overprovisioning and the higher cost of enterprise-class SSDs reflects the cost for added storage. The Network World article notes these characteristics in fine detail.

Harbaugh tested the Adaptec SSD controller/Intel SSD combo and drives or drive arrays from Apricorn, Compellent, Dot Hill, Fusionio, HP, and Ritek. The testbed was an HP ML370G5 server running Windows Server 2003 with external storage connected via Fibre Channel through a 2Gbps HP FC switch and the tests were run with IOmeter. Harbaugh notes that the Fusioio 32-Gbyte ioDrive and the HP StorageWorks IO Accelerator for blade servers (made by Fusionio) achieved the highest throughput in the tests. The Fusionio SSD delivered read and write throughputs of 706 and 456 Mbytes/sec respectively while the HP StorageWorks IO Accelerator delivered read and write throughputs on a blade server of 806 and 618 Mbytes/sec respectively. Both products delivered “excellent IOps, with no write cliff.” Note that the Fusionio drive costs $6,829.99 and the list price for HP StorageWorks IO Accelerator ranges from $4400 to 13,200 on the HP Web site for storage capacities ranging from 80 to 320 Gbytes. The tested 160-Gbyte HP accelerator lists for $7700. So performance comes at a price (nothing new there) that’s substantially higher than the SATA drives configured as HDD replacements.

Only the application developer can determine if high throughput and the absence of a write cliff is worth several thousand dollars. In many enterprise-class situations, the additional hardware cost is irrelevant. Online businesses such as Amazon.com have found that even a 1% increase in response time causes lost sales to the tune of millions of dollars because online customers are impatient and they bore easily. They will not wait long before wandering off, perhaps to a faster competitor. Large investment firms measure millisecond increases in online trading latency in terms of millions of dollars as well. The first trading firm to get a deal leaves competitors choking in the dust with no deal at all. So a few thousand dollars to avoid a sudden latency increase measured in tens or hundreds of milliseconds or even seconds is trivial insurance against large potential business losses.

The Network World article notes that one advantage these faster drives have is their use of the PCIe interface rather than the drive industry’s preferred SATA or SAS interfaces. The PCIe interface is closely coupled to the computer’s or server’s processor and can therefore provide very low latency and very high throughput, which is easily increased simply by adding parallel PCIe lanes. Several of the storage products including those from Fusionio and HP that were tested in this article employ PCIe interfaces to improve the storage subsystem’s performance.