A bit more than a week ago, HDD leader Seagate and NAND Flash leader Samsung jointly announced that they would cooperate on the development of an SSD controller. The announcement mentions “Seagate's leadership in enterprise storage technology” and “Samsung's flash memory technology specific to 30 nanometer-class MLC NAND.” There’s a little more information in a blog posted the same day by David Szabados, who manages the communication programs for Seagate's enterprise storage and emerging technology initiatives. Szabados writes:

“…it doesn’t matter whether we’re discussing SSDs or HDDs; engineers working with both technologies are most often tasked with limiting the number of data errors produced at the media. Think of it as the game of always looking to make perfect something that will always be imperfect to start with. Seagate has great expertise in minimizing errors on its media and its current enterprise HDDs are best-in-class in the area of error recovery.”

Later in his blog entry, Szabados writes:

“…today’s announcement references the use of Samsung’s 30 nanometer-class MLC (Multi-Level Cell) NAND as the technology base for the collaborative project. MLC NAND enables higher capacities at a lower cost, but it has not typically been a target technology for enterprise use due to having lower endurance. However, the controller technology that Seagate and Samsung develop together with its advanced error recovery and flash management, will enable more cost-effective and long-life products for the enterprise space.”

Clearly, as the industry turns to multiple bit/cell storage, error management, detection, and recovery will become extremely important aspects of economic SSD design. The company or companies that develop or purchase advanced error-management technologies that can make multiple-bit/cell NAND Flash devices reliable in targeted markets—whether consumer or enterprise—will have a real competitive advantage over companies that do not. So you can expect see increasingly advanced error coding using multiple error-detection and error-correction approaches employed with Flash devices to compensate for the decreasing reliability of Flash cells (SLC, MLC, and TLC) as lithographies shrink.