The rumor at the recent Flash Memory Summit held earlier this month was that HP was about to announce an agreement with a commercial semiconductor vendor to take the fabled memristor, heretofore an almost mythical memory element seen only by researchers within HP Labs, into production. The rumor got the announcement date and the vendor wrong, but it was essentially true. Today, HP and Hynix announced that they will jointly bring the memristor to the market as a commercial memory device. HP had previously announced experimental memristors with 1 nsec cycle times using 3nm (!) design rules. Even with those early experimental specs, the memristor looks mighty tempting as a potential heir to the DRAM throne. Couple in the memristor’s nonvolatility and you have a category killer.

Memristor memory from HP and Hynix now sports the moniker ReRAM for Resistive Random Access Memory. HP and Hynix will jointly develop new materials and process integration technology to transfer HP’s memristor technology from research to commercial development. Hynix will then implement the memristor technology in its R&D fab.

Toshiba announced today that it has initiated mass production of NAND Flash memories using 24nm process technology. The initial devices are MLC (2 bits/cell) 64-Gbit devices with Toggle-Mode DDR interfaces for high transfer speed. Toshiba also plans to make TLC (3 bits/cell) and 32-Gbit devices using this process technology. This announcement puts Toshiba ahead in the “20nm-class club.” Other members of the club include Samsung, making NAND Flash devices using what is considered to be a 27-nm process; Hynix, using what is believed to be a 26-nm process; and IM Flash (jointly owned by Intel and Micron), using a 25nm process. The use of “20nm-class” process technologies across the board by all of these vendors puts NAND Flash squarely at the front as a process-technology driver.

We’re still at the stage where there can be appreciable differences in the performance of various SSDs. In that light, Tom’s Hardware released performance test results on 17 different SSDs today. Some of the SSDs included in the tests are:

• Asax Leopard Hunt II (TS25M64, 128 Gbytes)
• Asax Server One 120 (200 Gbytes)
• Crucial RealSSD C300 (64 Gbytes)
• G.Skill Phoenix FM25S2S (100 Gbytes)
• G.Skill Phoenix Pro (120 Gbytes)
• Intel X25-M G2 (160 Gbytes)
• Intel X25-V (40 Gbytes)
• OCZ Vertex 2 (VTX100G, 100 Gbytes)
• OCZ Vertex 2 (E series, VTX2E120G, 120 Gbytes)
• OWC Mercury Extreme SSD (100 Gbytes)
• RunCore Kylin II SSD (100 Gbytes)
• Toshiba HG2 (256 Gbytes)
• Western Digital Silicon Edge Blue (256 Gbytes)

The article contains specifications and test results in mind-numbing detail. If you’re interested in that level of detail, go to the article using the link above. The conclusions are brief; Here are the highlights:

• The Crucial RealSSD C300 offers the best performance and the best performance per dollar per Gbyte of storage.
• All SSDs based on the SandForce SF-1200 controller deliver great throughput, stellar I/O performance, and low power consumption.
• Intel’s X25-M has been a great option for many months—and still is.
• Toshiba’s HG2 requires the least power to operate.
• Western Digital’s 256Gbyte Silicon Edge Blue did not fare well against the competition.
• Budget-sensitive users should consider the 64Gbyte Crucial RealSSD C300 and the Intel X25-V.

Last week saw the 22nd Hot Chips conference, held at held Stanford University, and one of the companies presenting their latest thoughts on “hot chips” was global networking leader Huawei. Sailesh Kumar presented some details on a network-processing chip currently under development at Huawei that is essentially “smart memory.” Such a chip is mostly memory—in this case, according to an EETimes article (http://www.eetimes.com/electronics-news/4206434/Huawei-smart-memory-chip) —32 Mbytes of IBM’s embedded DRAM (eDRAM) in 45nm process technology.

Now every chip designer knows that the most efficient way to place a large amount of memory on an ASIC is to put all of that memory in one large block with one memory controller, one set of address decoders, and one set of sense amps for the data. That’s the most efficient way to embed memory from a purely silicon perspective. However, that’s not how Huawei’s design team has architected this chip. Instead, the 32 Mbytes of eDRAM is split into 16 separate blocks and each block has its own attached processor, called an SM Engine. The sixteen SM engines communicate over a local interconnect grid that looks to be either a large crosspoint switch or a full-blown network on chip (NoC).

So why is Huawei not taking the most efficient approach from the silicon perspective. For a system designer, the answer is simple. Placing all of that memory in one block creates an artificial system bottleneck. With one large block of eDRAM, all 16 on-chip processors would need to access that memory through one memory interface. Certainly, it’s possible to add more interfaces to the memory block to create a multiport memory, but then the memory array itself would need to run faster. From a systems perspective, you achieve optimum balance with 16 processors, 16 memory blocks, and 16 memory interfaces. Such an approach boosts effective memory bandwidth by 16x, with some silicon overhead.

There are other benefits to this approach, however. One of the biggest benefits is that each of the 16 memory blocks is inherently locked to the processor as a private resource. There is no question of access arbitration and no possibility of nasty system-level bugs such as priority inversion, deadlock, or access-latency variation.

Network processing is one of those problems that is known to be “embarrassingly parallel.” Although there’s a torrent of packets entering the network processor, each packet needs a finite amount of processing. Cisco has already designed at least two processor-array chips that take the approach of giving individual processors responsibility for handling packets from birth to death: the 192-processor SPP and the Quantum Flow Processor with 40 quad-threaded processors. Now Huawei has taken a somewhat different approach along the same axis: fewer processors with more memory per processor and more threads per processor.

Within the problem context, why do this? After all, the smart memory approach flies in the face of conventional, contemporary ASIC design that couples an ASIC with big chunks of external, commodity SDRAM in the form of one or more DDR2 or DDR3 modules. This design approach is currently in favor because commodity SDRAM modules represent the absolute lowest cost per bit for any RAM available. Bandwidth is the reason for taking a different approach. To get the bandwidth needed in a multi-Gbit or Tbit router, you’d need several DDR channels, which incurs more silicon for memory controllers. Worse, you need more package pins to talk to each additional DDR channel and IC package technology advances far more slowly than Moore’s Law. You also need more power to talk to all of those DDR SDRAMs. Meanwhile, on-chip processing power and bandwidth are growing at a far faster pace than the bandwidth for external DDR memory interfaces.

Here are some small statistics from Huawei’s presentation to help you understand the nature of the memory-bandwidth problem for network processors:

1. A FIB (forwarding information base) lookup, used to determine a destination address, requires about six round-trip memory accesses (read/write).
2. An ACL (access control list) lookup, used to determine the type of handling a packet requires, needs about 20 round-trip memory accesses.
3. A hash-table lookup requires about four round-trip memory accesses.
4. Counters and policy policing require about four round-trip memory accesses.
5. Packet queue operations require about five round-trip memory accesses.

That’s a lot of memory accesses per processor and per packet. So then what’s the bottom line? Huawei’s presentation makes it clear. A large amount of distributed on-chip memory reduces pin, power, cost, and area by 10x. That’s a big enough number to get any system designer’s attention. In fact, says the Hot Chips presentation, this approach is the “only practical solution for 400Gbps” and beyond. Do you really need a more definitive statement than that?

A recent check of the Yahoo! Finance boards showed some skepticism about my previous statement that there were 200 SSD players in the market. Here’s a list of about 150 vendors compiled from various pages at www.storagesearch.com. It’s not a list of 200 vendors, but I don’t think it’s exhaustive either. Storagesearch has been published by Zsolt Kerekes since 1996. He’s an SSD analyst and his site aims to be comprehensive. It does contain a substantial amount of information.

• AboUnion
• ACARD Technology
• Active Media Products
• A-DATA
• Adaptec
• Addonics Technologies
• Adtron
• Advanced Media / RITEK / Traxdata
• Apacer
• Afaya
• Aitech Defense Systems
• Altec ComputerSysteme
• AMP
• Apacer
• APRO
• Asine
• Attorn
• Audavi
• Austin Semiconductor
• Avere Systems
• Barun Electronics
• BiTMICRO Networks
• Buffalo Technology
• Cactus Technologies
• Corsair
• CoreSolidStorage
• Curtis
• Curtiss-Wright
• Dane-Elec Memory
• DataDirect Networks
• Dataram
• DDRdrive
• Delkin Devices
• Density Dynamics
• Dolphin
• DTS
• Dynamic Solutions International
• EasyCo
• EDGE Tech
• Foremay
• Freecom Technologies
• Fujitsu
• Fusion-io
• GalaxyStor
• Gear6
• GIGA-BYTE Technology
• G.Skill
• Hagiwara Sys-Com
• Hitachi
• Hynix Semiconductor
• IEI Technology
• Imation
• InnoDisk
• Intel
• I/OMagic
• Iomega
• ioSafe
• Kaminario
• KingFast
• KingSpec
• Kingston Technology
• LaCie
• Lauron Technologies
• Lexar Media
• MagicRAM
• MemoCom
• Memoright
• Micro Memory
• Micron / Crucial
• Mtron
• Mushkin
• Myung Information Technologies
• Nanochip
• OWC
• OCZ Technology Group
• Oracle/Sun
• Panasonic
• Patriot Memory
• Phison Electronics
• Phoenix International
• PhotoFast
• Plextor
• Pliant Technology
• PLDS
• PNY Technologies
• PhotoFast
• PQI
• Pretec Electronics
• pureSilicon
• Real Ram Disk
• Renice Technology
• RunCore
• Samsung Electronics
• SandForce
• SanDisk
• Sans Digital
• SDK
• SeaChange International
• Seagate
• SEEK Systems
• Sharkoon
• Shining Technology
• Silicon Power
• Silicon Storage Technology
• SMART Modular Technologies
• Solid Access Technologies
• Solid Data Systems
• Solidata International Technologies
• Soliware
• SOYO
• Spansion
• Stealth.Com
• STEC
• Strontium
• Super Talent Technology
• Swissbit
• Taejin Infotech
• Targa Systems Division
• TDK
• Team Group
• Texas Memory Systems
• Third I/O
• TiGi
• Toshiba
• Transcend Information
• Trident Space & Defense
• Unigen
• Vanguard Rugged Storage
• Verbatim
• Viking Modular Solutions
• Violin Memory
• ViON
• Virident
• Virtium Technology
• VMETRO
• Walton Chaintech
• Western Digital
• White Electronic Designs
• Wintec
• XLC Disk

A fascinating Masters thesis written by Feng Xiong details the fabrication and testing of a phase-change memory (PCM) element using carbon nanotube FETs and “microbubbles” of GST to create extremely small, non-volatile memory elements. (GST is the chalcogenide glass material usually employed as the phase-change media in PCM and widely used as the active material in recordable CDs and DVDs.) Fusing a GST microbubble with a carbon nanotube FET produces an extremely small memory element with a measured programming current of 10 microamps—almost two orders of magnitude smaller than the figures published for the early commercial PCM devices just starting to appear after 40 years of PCM development. Feng Xiong is a Masters candidate in the Department of Electrical and Computer Engineering in the Graduate College of the University of Illinois at Urbana-Champaign and his work is pretty impressive.

Dropping the programming current of a PCM cell overcomes one of several major scalability problems associated with PCM. However, Xiong’s experiments are all about developing and characterizing one working PCM cell, not creating a process that can mass-produce billions of such cells on one chip. To do that, we still need to find ways to create carbon nanotubes at will, in exact sizes, placed regularly and precisely, billions of times per chip, chip after chip. We’re not there yet.

A bit more than a week ago, HDD leader Seagate and NAND Flash leader Samsung jointly announced that they would cooperate on the development of an SSD controller. The announcement mentions “Seagate's leadership in enterprise storage technology” and “Samsung's flash memory technology specific to 30 nanometer-class MLC NAND.” There’s a little more information in a blog posted the same day by David Szabados, who manages the communication programs for Seagate's enterprise storage and emerging technology initiatives. Szabados writes:

“…it doesn’t matter whether we’re discussing SSDs or HDDs; engineers working with both technologies are most often tasked with limiting the number of data errors produced at the media. Think of it as the game of always looking to make perfect something that will always be imperfect to start with. Seagate has great expertise in minimizing errors on its media and its current enterprise HDDs are best-in-class in the area of error recovery.”

Later in his blog entry, Szabados writes:

“…today’s announcement references the use of Samsung’s 30 nanometer-class MLC (Multi-Level Cell) NAND as the technology base for the collaborative project. MLC NAND enables higher capacities at a lower cost, but it has not typically been a target technology for enterprise use due to having lower endurance. However, the controller technology that Seagate and Samsung develop together with its advanced error recovery and flash management, will enable more cost-effective and long-life products for the enterprise space.”

Clearly, as the industry turns to multiple bit/cell storage, error management, detection, and recovery will become extremely important aspects of economic SSD design. The company or companies that develop or purchase advanced error-management technologies that can make multiple-bit/cell NAND Flash devices reliable in targeted markets—whether consumer or enterprise—will have a real competitive advantage over companies that do not. So you can expect see increasingly advanced error coding using multiple error-detection and error-correction approaches employed with Flash devices to compensate for the decreasing reliability of Flash cells (SLC, MLC, and TLC) as lithographies shrink.

Cadence’s Senior Manager of Technical Communications and a longtime EDA observer Richard Goering attended the recent Flash Memory Summit held last week in Santa Clara, California and came away with eight key ideas that closely tie memory to system design. The first four are:

• Memory may be the most important part of your system.
• You have to understand the end-user applications to choose a memory subsystem.
• Deep collaboration between OEMs and memory provides is becoming crucial.
• Existing memory technologies are running into limits.

For explanations of these first four ideas and to see the last four with their explanations, click here.