Taiwan Economic News reports that DRAM vendors will be bringing 4x nm process technologies on line during 2010 and 2011 to keep manufacturing profits up. According to P L Pai, vice president of Nanya Technology, DRAM chip makers are presently climbing the learning curve with 40nm process technologies and he says that the lead time of 40nm immersion tools averages nine months. Consequently, he predicts that production volumes for 4x nm DRAMs will be available in 2011. Pai also said that Samsung has already migrated to a 46nm process and Hynix is likely to successfully shift to a 4x nm process in the third quarter. According to the article, Nanya began pilot DRAM production in June using a 42nm process with two 4x nm immersion tools and will add two more 4x nm machines sometime in the second half of this year.

To get the latest technical and business information on DRAMs and DRAM manufacturing and to network with the movers and shakers of the DRAM industry, you really need to attend MemCon 2010 next month in Santa Clara, California. This event is open free to qualified individuals. To see the MemCon 2010 agenda, click here.

To register for MemCon 2010 immediately (which would be an excellent idea, by the way), click here.

June’s Microprocessor Report carries an article written by Editor-in-Chief Jim Turley that describes two new 32-bit microcontroller families from Freescale (formerly Motorola Semiconductor)—one family dubbed Kinetis featuring an ARM Cortex-M4 processor core and the other a revamped ColdFire processor architecture dubbed ColdFire+. Both microcontroller families feature a non-volatile, “Flash-like” memory technology dubbed FlexMemory that’s based on nanocrystal silicon dots rather than on polycrystalline silicon floating gates. Although these microcontrollers are the first to feature Freescale’s nanocrystal memory technology, the company has been developing this semiconductor memory technology since 2003 and it first discussed the technology at the 2005 International Electron Devices Meeting (IEDM). Nanocrystal memories have been discussed in the literature at least as far back as 1995, when IBM researchers at the Watson Research Center discussed the idea in a theoretical IEDM paper with some experimental results.

Flash-like nanocrystal memories offer several benefits over conventional Flash memories. In particular, the distributed nature of the electron storage in a planar, "thin-film" array of hemispherical silicon nanoparticles means that a gate-oxide defect will not drain the entire floating gate in a memory-storage transistor; only the nanoparticle(s) touching the defect are affected. Each nanoparticle holds only a “handful” of electrons, so loss of any one nanocrystal or even a few nanocrystals from leakage will not kill the memory cell. Consequently, nanocrystal memory cells are expected to be more robust than conventional Flash memory cells. Second, silicon nanocrystal fabrication employs a CVD (chemical vapor deposition) process and does not require the complexities of a dual-poly process so there may be some manufacturing-cost savings.

Freescale’s nanocrystals are hemispheres of silicon measuring roughly 10 to 15 nm in diameter and they’re spaced roughly 7 to 8 nm apart. They’re deposited in one planar layer within the gate-to-channel oxide, which must be formed in two steps: one thin layer on top of the channel that serves as the substrate for the nanocrystals and then a thicker covering layer that insulates the nanocrystals from each other and from the transistor’s gate. These geometries result in a storage distribution of approximately 200 nanocrystals per bit in the 90nm process technology Freescale uses to fabricate the new ARM- and ColdFire-based microcontroller families, so the loss of a few nanocrystals to oxide defects will not affect transistor thresholds very much. At the 65nm and 45nm process nodes, which FreeScale currently cannot build, there would be fewer than 100 such nanocrystals per bit, but that’s still a sufficient number to create a memory cell with robust characteristics.

However, the robustness of the nanocrystal memory is not the only aspect that has caused Freescale to employ the technology in these new microcontroller families. In total, the nanocrystals forming the floating gate of the FlexMemory cell contain less mass than a conventional Flash floating gate, so the nanocrystals require less tunneling write current. As a result, nanocrystal memory requires less programming current, cutting the amount of power needed to write a bit in the memory. In addition, the nanocrystal FlexMemory write time is approximately 100 microseconds, which is about 10x faster than Flash memory. That too is due to the lower “mass” of the nanocrystal “floating gate” and is a highly desirable feature. In fact, Freescale exploits the extra speed by allowing the processor to treat the nanocrystal memory like Flash EEPROM or, through emulation, embedded EEPROM. The emulation ability is derived from FlexMemory’s faster speed and write/erase durability.

FlexMemory may appear in Freescale’s older microcontroller families such as the 56800 DSP-centric and the PowerPC-based MPC5xx microcontroller families. In addition, Freescale appears to be interested in licensing the nanocrystal memory technology, although the company has yet to announce a licensee.

Intel recently announced that Best Buy is now carrying its retail-boxed X25-M (mainstream) and X25-V (value) SSDs. The 80-Gbyte X25-M sells for $229.99 and the 40-Gbyte X25-V sells for $129.99. Neither of these drives is large enough to act as a replacement drive in most of today’s notebook or even netbook computers. However, they can serve as boot and application drives to help speed boot and load times. Nevertheless, the appearance of SSDs in retail locations, starting with Best Buy indicates just how mainstream SSDs are becoming. It wasn’t that many years ago that retail locations didn’t offer HDDs. You had to order them over the Internet unless you lived near a Fry’s in Silicon Valley, take a train to the Akihabara in Tokyo, or visit the Yongsan Electronics Market in Seoul. Now HDDs routinely appear in the color ads in Sunday newspapers and they are a routine retail item. Intel’s announcement of Best Buy as a retail channel indicates that SSDs are now starting down that same path.

The idea of 3D wafer stacking isn’t new. I wrote an article about 3D assembly of silicon die and entire wafers using through-silicon vias (TSVs) more than 20 years ago in an EDN series titled Decade 90, but it was only an experimental technology way back then. Over the past 10 years, SIP or system-in-package assembly techniques have taken the compact mobile product world by storm, particularly in products such as cell phones where reduced component volume translates directly into reduced end-product size and a corresponding increase in the perceived value of the end-product. Existing techniques rely heavily on wire-bond stitching or intermediate carrier boards to implement the 3D assembly. It’s clear that more automated, lower-cost die-stacking and -attachment techniques are in the industry’s immediate future and there’s no better indication of that imminent advance than the recent cooperative 3D-assembly development announcement by DRAM-maker Elpida, Taiwan assembly house Powertech Technology Inc (PTI), and silicon foundry UMC. The three companies plan to work together to develop more automated, less costly methods for designing ICs that incorporate TSVs and for packaging the resulting chips into 3D assemblies. The announcement specifically mentions targeting 28nm as well as other process nodes.

For its part, Elpida developed an 8-bit DRAM based on TSV technology last year. The company claims that the TSV interconnects allow much wider interconnect between the DRAM and the associated SOC, which can increase the bandwidth between the DRAM and the SOC, lower the transfer rate and therefore lower the power consumption (because more bits are transferred per clock), or both. However, to be useful, Elpida’s TSV-based DRAMs need appropriately designed SOCs that will mate with the DRAMs. Developing the technology that supports the design and manufacture of such SOCs is UMC’s responsibility in this partnership.

Bonding these chips together and packaging them is PTI’s responsibility. PTI already claims to have been developing its 3D-assembly expertise since 2007 and has begun working with silicon die as thin as 50um. The company has already worked on SIP assemblies that stack as many as eight die in one package and it is working on the ability to stack 16 die in one low-profile package. These existing 3D assemblies do not use TSV technology. Developing TSV assembly techniques is the next step for PTI, working in conjunction with Elpida and UMC.

SanDisk has just unveiled a WORM (write-once, read mostly) variant of the ubiquitous SD Flash memory card that’s intended for applications where stored data must be tamper-proof and unalterable. Such situations include video, image, audio and other forms of legal evidence; business and tax records; voting records; and medical records. In all such cases, all parties must believe that the data is exactly as it should be and that there’s no chance that it’s been tampered with. Lives and careers are at stake in most of these applications. The WORM SD card looks like a conventional SD card but it will only work in specially configured SD card writers. Any SD card reader can read one of these WORM SD cards.

Currently, the SanDisk site points to an OEM sales email address for anyone interested in this technology. However, SanDisk may be ignoring (or at least momentarily ignoring) a large number of amateur and pro photographers who might well want to use their SD cards like film, with no possibility of image erasure. With the cost of SD card storage so low, it’s already much cheaper than film ever was per image, so that it’s now quite realistic to think of using write-once Flash media that can never, ever be erased, no matter how hard you try.

MemCon is coming up next month, on July 28 in Santa Clara, California. Here’s a list of presentations and panels you’ll see. But only if you register. Register here.

Memory Market Outlook
Recurring Memory: Cycle Gathers Profit Momentum after Huge 2008 - 2009 Losses
Lane Mason, Memory Market Analyst

Emerging DRAM Technology: A 3D Perspective
Arun Kamat, VP Marketing
Hynix

Designing High Efficiency DDR3 Memory Controllers with today’s FPGAs
Adrian Cosoroaba, Technical Marketing Manager
Xilinx

Counterpoint: Is DDR3 Always the Best Choice?
Marc Greenberg, Director, Technical Marketing
Denali Software, Inc.

High Speed DRAM Packaging for DDR3 and beyond
Richard Crisp, Director Semiconductor Technology & Applications
Tessera

Overcoming Obstacles to Closing Timing for DDR3-1600 and Beyond
John Ellis, Sr. Staff R&D Engineer
Synopsys

High Speed Speed DDR3 for 1600 Mbps Wirebond and 2133 Mbps Flipchip Implementations
Ali Burney, Director of Marketing
Mosys, Inc.

DRAM in the Driver's Seat: Why Demand is Outpacing Projections
Jim Elliott, VP - Memory Marketing & Product Planning
Samsung

Analyst Forecast Panel
Moderator: Steve Leibson, Denali Software
Panelists:
Jim Cantore, JLC Associates
Lane Mason, Memory Analyst
Jim Handy, Objective Analysis

Challenges and Solutions for GHz DDR3 Memory Interface Design
Arun Vaidyanath, Sr. Engineering Manager
Rambus

RLDRAM and the NetFPGA 10G Project
Brian Gross, Applications Engineer
Micron Technology

James Hongyi Zeng, PhD Candidate
Stanford University

Synthesizable DDR1600 PHYs
Mike McKeon, Director, PHY Technology
Denali Software, Inc.

Serial Port Memory: Bandwidth is Not Just for PCs Anymore
Alan Ruberg, Systems Architect
SPMT, LLC

A PVT Compensating Read Data Capture Solution for DDR Memory Interfaces
Cheng Kong, Principal Engineer
LSI Corporation

Next Generation Design and Test for Next Generation Flash, Mobile and System Memory
Perry Keller, Standards & Applications Program Manager
Agilent Technologies

Panel Session: Memory Interfaces: What Comes after DDR3?

Moderator: Lane Mason, Memory Market Analyst

Panelists:
Wendy Elsaser, Denali Software
Bill Gervasi, Discobolus Design
Judy Chen, Rambus
Jim Venable, SPMT Consortium

Panel Session: Future Memory: What Will Replace DRAM?

Moderator: Steve Leibson, Denali Software

Panelists:
Bob Merrit, Convergent Semi
Barry Hoberman, Crocus
Marc Greenberg, Denali Software
Ed Doller, Micron

Remember, register here.

Today, Xilinx unveiled three new series of FPGAs all based on 28nm process technology from Samsung and TSMC. The three families are called the Virtex-7, Kintex-7, and Artix-7 series. All three FPGA families feature programmable I/O drivers with I/O voltages as low as 1.2V, which theoretically permits the use of all advanced, single-ended SDRAM interfaces such as the low-voltage LPDDR2 and high-speed DDR3-2133 memory interfaces. Devices in the low-end Artix-7 FPGA family, packaged in low-cost wire-bond packages, have as many as 450 I/O pins. The middle Kintex-7 FPGA family, available in flip-chip packages, have as many as 500 I/O pins and the high-end Virtex-7 FPGA devices have as many as 1200 I/O pins. The Artix-7 and Kintex-7 FPGAs are largely differentiated by performance (with some larger Kintex-7 devices offered) and unit price. The Kintex-7 and Virtex-7 FPGAs are differentiated by gate and I/O capacity and unit price.

Xilinx has based all of the -7 FPGA devices on a very advanced 28nm process technology that reduces electron tunneling through the gate dielectric using a halfnium-dioxide high-k, metal-gate (HKMG) FET gate stack to replace the more conventional Poly/SiON (polysilicon-gate with silicon oxynitride gate dielectric) stack. The hafnium-dioxide gate insulator reverses the trend towards thinner and thinner gate oxides and increasing gate leakage, which first started to cause problems at the 90nm process node. The increasing amount of leakage at due to tunneling at nanometer lithographies finally drove leakage currents up to unacceptable levels at 28nm for Xilinx. Xilinx observed that usable performance from shrinking device geometries was nonexistent by the 28nm node using the conventional FET gate stack so the company has adopted a more advanced 28nm process technology to combat the rise in static and dynamic power.

The resulting 28nm process technology allowed Xilinx to introduce three separate classes of -7 FPGA:

Artix-7: with 20% better performance, 50% lower power consumption, and 35% lower cost than the company’s Spartan-6 FPGAs.

Kintex-7: with double the performance of the previous -6 FPGA generation, in low-cost packaging.

Virtex-7: with double the performance of the previous -6 FPGA generation and large numbers of I/O pins.

All three of the new Xilinx -7 FPGA families share a common architecture, making it easier to move designs from one -7 FPGA family without a redesign to the next -7 FPGA family based on performance and cost criteria. The -7 FPGA family design tools also do a more thorough job of evaluating opportunities for fine-grain clock gating, which can reduce dynamic power by as much as 20%.

Devices in the three FPGA families are scheduled to become available early in 2011.

Taiwan DRAM maker ProMOS has just announced successful fabrication of 1-Gbit DDR3 SDRAMs using Elpida’s 63nm (a 65nm shrink) fabrication process, transferred to ProMOS under a strategic partnership between the two companies that was initiated at the end of 2009. The 63nm process is up and running at ProMOS’ Taichung fab and the first trial lot of devices meets parametrics, signifying successful transfer of the 63nm process technology from Elpida. According to the ProMOS release, “Engineers from the two companies have been working closely in the past couple months to adjust and experiment process recipes to account for the vast differences in manufacturing equipment between the two companies.” Significantly, ProMOS release claims that “The chip size of this 1Gb DDR3, designed in 63nm, is as small as the chip sizes of other companies’ products, designed in 5Xnm technologies.” Because chip size directly affects device cost, this is indeed a significant achievement and advance for ProMOS and a real advantage in the hotly competitive landscape of SDRAM manufacture.

Anyone with experience in advanced IC lithography and manufacturing processes knows that the task of process transfer gets exponentially harder when transferring the process from one set of manufacturing equipment to a different set. That’s why leading semi vendor Intel employs a “Copy Exact” process-development policy that replicates all the elements of a fab, down to the “color of the walls” as a Microsoft manager has quipped in the past.