Engineering Luminary Discusses SoC Development with High-Speed Interface Solutions

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Brian Gardner, vice president of IP products at Denali Software, Inc., will speak on a panel titled, "Silicon Subsystems: How to Develop SoCs Faster and With Lower Risk," during the Intellectual Property (IP) Symposium, an event sponsored CMP. The panel session will be held Tuesday, April 15, at the Fairmont Hotel in San Jose, California. This panel addresses key areas pertaining to system-on-chip (SoC) development such as integration issues, improving data throughput, and lowering schedule risks. This panel will appeal to systems architects, SoC project managers, senior engineering and engineering management including directors and vice presidents of Engineering, Chief Technology Officers, Fellows, and members of Technical Staff.

About Denali Software

Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and semiconductor intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

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Denali and the Denali logo are trademarks of Denali Software Inc. All other trademarks are the property of their respective owners.

For more information, contact:

Editorial Contact:
Pierre Golde
Denali Software Inc.
650.461.7262
pgolde@denali.com

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