USB 3.0 Design and Verification Teams to Benefit from Pre-silicon Compliance and Interoperability Verification IP

SUNNYVALE, Calif., November 10, 2008 — Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its PureSpec™ verification intellectual property (VIP) product now supports the USB 3.0 specification from the USB 3.0 Promoter Group , allowing device and system designers to begin advanced USB 3.0 development. Denali’s PureSpec USB VIP product provides both design and verification engineers with a high-quality solution for modeling, simulating, and verifying designs that utilize the latest USB interface specification, enabling them to accelerate the design and verification of USB devices and systems.

“Denali has been a long-time supporter of USB technology and provider of verification IP solutions,” said Jeff Ravencraft, USB-IF president and chairman. “We are pleased to see this announcement from Denali, supporting the USB 3.0 specification, as it will help developers bring SuperSpeed USB products to market quickly and support compliance to the USB 3.0 specification with their USB VIP solutions.”

Denali's PureSpec VIP software for the USB interface supports the next-generation USB technology and specification as it continues to evolve. The USB 3.0 specification offers over 10x performance improvement and is fully backwards compatible with USB 2.0.

“Our customers are thrilled that we have enabled USB VIP for the next generation of USB, and thus can leverage Denali’s tools, experience and support with PCI Express and USB 2.0 to take advantage of the new SuperSpeed USB protocol,” states Sanjiv Kumar, director, Verification Products at Denali Software. “Our verification IP products not only support the next-generation interface requirements for design and verification of SuperSpeed USB devices and systems, but accelerate our customers’ design cycles time to market.”

About PureSpec USB 3.0 Verification IP
Denali’s PureSpec is the most widely-used verification IP product for verifying compliance and compatibility of USB designs. All PureSpec products are directly integrated into all popular EDA languages and verification environments including: Verilog, SystemVerilog, VHDL, C/C++, SystemC, 'e', OpenVERA. Quality, completeness and seamless integration with all modern verification environments, e.g., OVM, VMM, eRM, etc., make PureSpec the solution of choice for functional verification and interoperability validation of USB designs. A solid product platform, dedicated customer support, and unmatched EDA modeling and verification expertise make PureSpec USB the best-in-class verification IP solution. For more information about PureSpec USB, visit: www.denali.com/usb3.

About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.
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Denali and Denali Software are registered trademarks of Denali Software, Inc. PureSpec is a trademarks of Denali Software, Inc. All other trademarks are of their respective owners.

DFI Specification Available at the New Community Website Aimed At Growing DFI Ecosystem

SUNNYVALE, Calif., October 27, 2008 – Denali Software, Inc., today, as one of the DDR PHY Interface (DFI) specification participating members, announced the availability of the preliminary version of the DFI specification 2.1. The DFI specification extends support to the latest LPDDR2 memory technology and enables new features including frequency change support and low-power PHY options. The collaborative technical working group includes representatives from ARM, Denali, Intel, LSI, Samsung, and STMicroelectronics. This technical group is enhancing the specification with several low-power features aimed at speeding LPDDR memory system design and integration, and reducing verification costs. The preliminary DFI specification 2.1, now available, is just one of the many resources found on the growing DFI ecosystem community website. The website highlights leading DDR DRAM IP and service providers and discusses the upcoming DFI Forum keynote address by Bryan Jones from Intel on Tuesday, October 28 at the Academy Hills in Tokyo, Japan.

“As the migration to LPDDR2 memory and low power continues, there is a need to meet the demand for higher density, speed and lower power,” said John MacLaren, chair of DFI Technical Committee and senior staff engineer at Denali. “The latest DFI features will be well suited for low power and embedded system designs which target applications such as cell phones, ultra-mobile PCs and consumer applications.”

The DFI specification 2.1 enables a new low-power PHY interface that enables the controller to provide information to the PHY about the state of the system. This feature allows the PHY to take advantage of "down-time" by disabling various power consuming features of the PHY, as appropriate, for the state of the system. The new frequency change feature enables the controller to inform the PHY when a frequency change will occur and simplifies the frequency change process and the integration of devices that support this functionality.

“There is a rapid rate of adoption of this specification throughout the industry with over 3,000 downloads of the specification to date,” Bryan Jones, Corporate External IP Management, Mobility Group for Intel Corporation said. “I am looking forward to focusing on continued expansion of the ecosystem as well as on the DDR4 specification next year.”

About the DFI Specification
The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, its community, activities and how to participate, visit: www.ddr-phy.org.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions and platforms for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products, and services is available at www.denali.com.
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All trademarks are property of their respective owners.

Dr. Stephen Oh to Serve as Vice President of Platform Business Development

SUNNYVALE, Calif., October 14, 2008 – Denali Software, Inc., today announced that Dr. Stephen Oh has joined the company as vice president of Platform Business Development. With over 19 years of experience in high-growth, high-technology companies, Dr. Oh was most recently CEO of Solex Semiconductor and held executive and management positions at Samsung Semiconductor, Agere Systems, National Semiconductor and Texas Instruments. During his tenure as head of its multimedia lab within the SoC R&D center and vice president of the application processor development team, Samsung Semiconductor achieved a major share in the navigation and portable music player markets. At Denali, he is directly responsible for Denali's platform technologies, including FlashPoint, and developing long-term relationships with Denali's memory and storage partners.

“It’s a great win for Denali to have someone of Stephen’s caliber join our leadership team. He brings a valuable combination of experience, credentials and understanding of Denali’s next-generation NAND-based applications solutions,” said Denali Software’s president and CEO Sanjay Srivastava. “Stephen’s demonstrated business and technical leadership will be invaluable as we continue to grow our fully integrated, NAND-based platform solutions.”

“Denali has an excellent reputation for its investment in its customers, its people and its technology,” states Dr. Stephen Oh. “Together, we will expand Denali’s leadership position into the consumer market place with state-of-the-art flash cache and SSD products, solutions and services.”

Dr. Oh is a graduate of Purdue University where he received three degrees, a Ph.D., Masters and Bachelor of Science in electrical engineering.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and semiconductor intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

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Denali and Denali Software are registered trademarks of Denali Software, Inc. All other trademarks are of their respective owners.

Denali’s Configurable DDR2/3 DRAM, PHY, and Verification IP Products Enable
Siverge Networks to Optimize Performance in Network Convergence Processor

SUNNYVALE, Calif., September 23, 2008 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Siverge Networks, a fabless semiconductor company focused on the packet evolution in carrier networks, has adopted Denali’s Databahn™ DDR2/3 memory controller IP, integrated PHY and MMAV™ for their high-performance ASIC chip. Siverge’s next-generation high-performance network processors allow for larger bandwidth and convergence of different protocols across networking systems and multiservice capabilities. Denali’s design IP, integrated PHY, and verification IP accelerates Siverge’s designers’ ability to design DDR2/3 memory systems, lower their integration risk, and speed their time-to-market for their new convergence chip.

“Denali Software, our IP vendor of choice, has provided us a high-quality configurable DDR2 IP solution, and helped us achieve our design and performance requirements which were critical to our time-to-market schedule,” said Uzi Zangi, vice president of Research and Development at Siverge Networks. “Our new convergence family of devices (code name Griffin) will support a large number of different interfaces, a huge number of different channels at various speeds and a uniquely wide range of protocols, thus meeting the needs of many key manufacturer and solution providers of all types of transport systems (wireline and wireless), switches and routers, multiservice switches and mobile RNC and BSC systems.”

The Databahn product provides a comprehensive infrastructure for configuring, analyzing, and generating the optimal memory controller for any given application. Denali’s Databahn combination DDR2/DDR3 memory controllers and Denali’s Databahn PHY products achieve speeds up to 1600 Mbps. Together, they offer a powerful, multi-port solution with configurable features and functionality to satisfy system performance requirements, significantly reducing integration and interoperability risks.

Siverge Networks’ Griffin (SV36xx) family of devices is Siverge’s flagship product family. Griffin family of devices re-defines the price, performance, power, functionality in the layer 1, layer 2 and layer 3 telecommunication market. Some members in Griffin family are unique ‘any port, any service, any system, and any network devices', targeted for next-generation transport systems as well switches and routers, multiservice switches, and Base Station Controller and Radio Network Controller systems. Other members are providing specific functionality and are introducing a refreshing cost reduction together with revolutionary integration level and without compromising feature. All of the Griffin family devices are package, pin, and software compatible enabling huge savings in research and development as well as inventory and maintenance: “one design, many (different) linecards and systems.”

“High-quality IP is essential to solving DDR2/3 memory system requirements, especially when dealing with sophisticated and high-throughput applications,” said Marc Greenberg, technical marketing director at Denali Software. “With our design IP products, which include support for the latest DDR2/3 specifications, we are providing customers with flexible memory systems, reducing their design risks, and enabling seamless integration into their system environment. We also realize the importance of providing a complete IP solution that helps to ensure that Siverge will be able to meet aggressive schedules for their designs and we are pleased to be working with Siverge to achieve this.”

About Databahn Solutions
Denali’s Databahn DDR-DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1/2/3, and LP-DDR1/2 devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification testbench, static timing analysis (STA) scripts, programmable register settings, and documentation. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/products/dram.

About MMAV
Denali's MMAV product is the industry's de-facto standard solution for modeling and simulating memory during functional verification. MMAV has been used in thousands of designs to ensure correct and optimal behavior and timing between the system design and off-chip memory devices. MMAV utilizes a powerful and effective approach to modeling memory. MMAV 2008 is available immediately. Additional MMAV 2008 information and an evaluation can be requested at: http://www.denali.com/mmav.

About Siverge Networks
Siverge Networks is a pioneering fabless semiconductor company at the forefront of networking technology. Siverge has developed unique core technology enabling OEMs to build low-cost high-speed packet based communication systems for fast expanding Carrier Networks. Siverge's patent-pending Packet Transport SoC re-defines the technology limits of networking devices by integrating 10x more functionality and channel/port count. Siverge devices enable exceptionally high capacity, true multi-service solutions and system consolidation for Fixed and Mobile Backhauling Networks. The company is headquartered in Herzelia (Israel) with an office in Orange County, CA (US). The company was founded in 2005 and is privately held. Website:
http://www.siverge.com/.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and semiconductor intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.
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Denali and Denali Software are registered trademarks of Denali Software, Inc. Databahn and MMAV are trademarks of Denali Software, Inc. All other trademarks are of their respective owners.

High-Quality Verification IP Provides Pre-silicon Compliance and Interoperability Verification and Faster TTM to Design Teams Beginning Early Gen 3 Development

SUNNYVALE, Calif., September 3, 2008 — Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced the availability of PureSpec™ PCI Express™ (PCIe) verification intellectual property (VIP) product which now supports the latest version of the Gen 3 specifications from the PCI-Special Interest Group (PCI-SIG®), allowing chip designers to begin early Gen 3 development. Denali’s PureSpec PCIe VIP product, a complete solution for modeling and verifying pre-silicon compliance and interoperability for PCIe designs, enables engineers to accelerate the design and verification of PCIe systems, and speed overall deployment of PCI Express technology.

“Having verification IP from Denali this early for the PCI Express 3.0 specification will give developers a chance to work with the latest in interconnect standards,” said John Wiedemeier, PCI Express Tools product marketing manager at LeCroy Corporation. “There is no doubt that companies, like Denali and LeCroy, will help enable the transition to PCI Express 3.0 technology with their industry-leading PCI Express solutions. Denali's PCI Express IP and LeCroy's protocol analysis tools reduce integration issues and speeds time-to-market.”

Denali's PureSpec verification IP software for the PCI Express protocol keeps pace with the PCI Express technology and specification as it continues to evolve. The upcoming PCIe 3.0 specification is the next evolution of PCIe technology and includes interconnect performance improvements, full compatibility with prior generations, and PCIe 1.x and 2.0 cards will seamlessly plug into PCIe 3.0-capable slots. All PCIe 3.0 cards will plug into PCIe 1.x and PCIe 2.0-capable slots. The PCIe 3.0 specification removes the requirement for 8b/10b encoding and uses it uses a 128/130 code and physical layer encapsulation.

“Our customers depend on high-quality verification IP solutions that are in step with the latest revisions from the PCI-SIG and we look forward to providing them the highest level of technology expertise,” states Sanjiv Kumar, director, Verification Products at Denali Software. “Our verification IP products not only support the next-generation protocol requirements for design and verification of PCI Express systems, but accelerate our customers’ design cycles and provide them with a clear roadmap for incorporating the latest specifications for their deployment of PCI Express technology.”

About PureSpec PCIe Verification IP
Denali’s PureSpec is the most widely used verification IP product for PCIe technology; over 250 PCIe designs have been validated using PureSpec verification IP. All PureSpec products are directly integrated into all popular EDA languages and verification environments including: Verilog, SystemVerilog, VHDL, C/C++, SystemC, 'e', OpenVERA. Quality, completeness and seamless integration with all modern verification environments, e.g., OVM, VMM, eRM, etc., make PureSpec the solution of choice for functional verification and interoperability validation of PCIe designs. For more information about PureSpec, visit: https://www.denali.com/purespec.

About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.
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Denali and Denali Software are registered trademarks of Denali Software, Inc. PureSpec is a trademarks of Denali Software, Inc. All other trademarks are of their respective owners.

FlashPoint Platform Supports ONFi 2.0 NAND Flash Technology for
PCIe-based Memory Systems

SUNNYVALE, Calif., July 31, 2008 — Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its Databahn™ memory controller IP and MMAV™ simulation models for design and verification, now include comprehensive support for Open NAND Flash Interface (ONFi) 2.0 device technology. Denali’s FlashPoint™ product, an end-to-end chip design platform for implementing memory sub-systems, also supports ONFi 2.0 device technology for PCI Express (PCIe) based Cache, and SSD applications.

“We are very pleased to announce support for the ONFi 2.0 device technology with memory controller designs and high-quality simulation models,” states Kevin Silver, vice president of Business Development at Denali Software. “Early availability of device models and memory controller products is consistent with our goal to speed the adoption of new memory technologies, and ultimately enable more efficient and high-performance memory subsystem design. The Flashpoint platform is a good example of how Denali’s taking this value proposition one step further by providing customers with a complete chip design, an end-to-end solution for PCIe-based flash memory systems, and as in this case, leverages all the features and functionality of ONFi 2.0 devices.”

“We are very pleased with the success of moving the ONFi 2.0 NAND Flash specification towards industry-wide support,” said Amber Huffman, Principal Engineer, Storage Technologies Group at Intel, and Technical Architect within the ONFi working group. “Enabling technologies, such as Denali’s commercial design and verification products, help to speed industry adoption of ONFi 2.0 devices in next-generation NAND Flash-based end applications.”

About MMAV 2008
Denali's MMAV product is the industry's de-facto standard solution for modeling and simulating memory for functional verification. MMAV has been used in thousands of designs to ensure correct and optimal behavior and timing between the system design and off-chip memory devices. MMAV utilizes a powerful and effective approach to modeling memory. MMAV 2008 support for ONFi 2.0 is available immediately. Additional MMAV 2008 information, including evaluation licenses, can be requested at: http://www.denali.com/mmav.

About Databahn Solutions
Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, and LP-DDR devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification test bench, static timing analysis (STA) scripts, programmable register settings, documentation, I/O pads and packaging. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/dram.

About FlashPoint
The FlashPoint platform is a complete system design, providing a PCI Express (PCIe) interface to high-performance NAND Flash memory. The platform uses a unique design configuration engine that enables the system to be tuned for optimal performance with differentiating features for a range of products, including PC cache modules, solid state drives (SSD), and ExpressCard™ devices. More information about the FlashPoint platform and its performance features can be accessed at: https://www.denali.com/flashpoint.

About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

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Denali and Denali Software are registered trademarks of Denali Software, Inc. Databahn, FlashPoint, and MMAV are trademarks of Denali Software, Inc. All other trademarks are of their respective owners.

Industry-Leading Verification IP Solution Provides Full Specification Support of PCI-SIG IOV Technology Standard

SUNNYVALE, Calif., July 31, 2008 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its PureSpec™ PCI Express® (PCIe) verification intellectual property (VIP) product, supports the complete PCI-SIG® I/O Virtualization (IOV) specifications, now including Multi-Root IOV(MR-IOV). The PCI-SIG IOV suite of specifications minimizes system hardware and software requirements, allowing the simultaneous sharing of peripherals across multiple microprocessors and operating systems, increasing the performance of virtualized systems and enabling significant power savings. Denali’s PureSpec VIP allows verification engineers to verify their next-generation designs, ranging from server processors and network chipset to communication systems, for compliance to the latest PCIe standard, and take advantage of the newest set of IOV technologies.

“PCI-SIG recently announced its suite of specifications for I/O virtualization designed to improve performance and lower CPU/memory consumption,” states Al Yanes, PCI-SIG President. “PCI-SIG values Denali’s contributions to the industry adoption of our specifications through its work to develop IP products that support the suite of PCI-SIG IOV standards.”

“Denali understands the challenges facing design teams, including the complex IOV requirements for complex server, switch and router systems,” states Sanjiv Kumar, director of VIP products at Denali Software. “As a provider of PCIe verification IP, our customers use our complete high-quality verification IP that addresses all aspects of the latest PCI-SIG specification. Their designs can meet PCI-SIG IOV compliance and help verification engineers significantly shorten their validation cycle.”

About Denali PureSpec
Denali's PureSpec verification IP software for PCIe is the most widely used solution for verifying functionality, compliance and interoperability of PCIe designs at the pre-silicon stage of chip or IP core development. PureSpec supports the latest PCI-SIG specifications for Address Translation Service, Single-Root and Multi-Root I/OV, including configuration spaces (physical function, virtual function and base function), Alternative Routing-ID interpretation, Functional Level Reset (FLR), and PCI Manager (PCIM) capabilities. For more info about PureSpec and its benefits in your next design, visit https://www.denali.com/vip.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

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Denali and Denali Software are registered trademarks of Denali Software, Inc. PureSpec is a trademark of Denali Software, Inc. All other trademarks are of their respective owners.

Expanded Working Group to Deliver Next Version of DDR PHY Specification Minimizing Design and Integration Cost Benefits with Reusable IP

SUNNYVALE, Calif., July 23, 2008 – Denali Software, Inc., today, as one of the DDR PHY Interface (DFI) specification participating members including ARM, Denali, Intel, and Samsung, announced that LSI Corporation and STMicroelectronics have joined the collaborative technical working group for the industry standard DDR-PHY Interface (DFI) specification, which simplifies the interoperability between the memory controller and PHY. Representatives from these industry-leading companies make up the collaborative technical working group, which plan to contribute to improvements and enhancements in the next version of the DFI specification. With the expanded technical working group, including LSI and STMicroelectronics, the ongoing development of the specification will continue to benefit PHY providers, chip architects and memory controller vendors, speeding their DDR memory system design and integration, reducing significant verification costs.

“Industry-accepted interface specifications simplify development and facilitate interoperability,” said Don Friedberg, director of Foundation IP Solutions at LSI Corporation. “The DDR-PHY Interface specification will help streamline the integration of memory interface PHYs with high-performance controllers.”

“STMicroelectronics is a strong promoter of open industry standards. Parallel DRAM interfaces are increasingly becoming a performance driver for many of our system-on-chip products in computer peripheral, consumer, telecom, and wireless applications,” said Pierre Dautriche, AMS and PHY IPs director at STMicroelectronics. “It is therefore natural that ST joins the DFI standardization body, which will benefit our customers with higher performance in our DDR interfaces.”

This current version of the specification, DFI 2.0, available through a click-thru license at: www.ddr-phy.org, supports DDR1, DDR2, Mobile, and DDR3 memory; adds read, write, and gate training interfaces; and improves upon the interoperability features between the memory controller and a DDR PHY. The official version of the specification has been based on the 1.0 foundation of the common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs. This specification allows designers a standard that has wide industry acceptance and ensures that the controller and PHY will work optimally together and no changes will be required to the hardened logic, resulting in reduced cost, time-to-market, and increasing reusable system IP. Further DDR DRAM and PHY technical discussions, presentations, and supporting technologies will be highlighted during the upcoming MemCon event, “The Technology Roadmap for Memory and Storage,” in Santa Clara, CA., from July 21-24.

“LSI and STMicroelectronics coming aboard as technical contributors to the next DFI specification represent the significant awareness and the importance of a standard interface between the controller and PHY,” said Bryan Jones, who oversees Corporate External IP Management for Intel’s Mobility Group. “Amidst the growing community of technology experts and interface users, the contributions from the expanded technical team will increase further industry adoption, technical advancement, and exciting opportunities.”

“With these new additions to the contributing technical committee, we look forward to improvements in the next version of the existing specification,” said Brian Gardner, vice president of IP products at Denali. “The industry will continue to benefit from memory controllers and PHYs that fall in line with the specification, providing enhanced interoperability and high performance.”

About the DFI Specification
The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, visit: www.ddr-phy.org.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions and platforms for deploying PCI Express®, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products, and services is available at www.denali.com.
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PCI Express is a registered trademark of PCI-SIG. All trademarks are property of their respective owners.

First Provider of Memory Controller and PHY Solution to Support LPDDR2 in Next-Generation Mobile and Embedded Applications

SUNNYVALE, Calif., July 21, 2008 — Denali, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its Databahn™ memory controller and PHY IP supports the pre-released LPDDR2 specification, as currently defined by JEDEC - the leading developer of standards for the solid-state industry. Chip designers and system architects desiring to upgrade to LPDDR2 can learn more about Denali’s new upcoming LPDDR2 offering, which will include both varieties of SDRAM (S2/S4) in the memory controller and PHY IP and support for Non-Volatile Memory (NVM) by attending the MemCon presentation, “Next-Generation Low-Power LPDDR2 Memories: How to Use Them in Your Mobile and Embedded Designs” at 1:30pm on Wednesday, July 23 in Santa Clara, CA. Denali’s Databahn LPDDR2 memory controller and PHY will be well suited for low power and embedded system designs which target applications as cell phones, ultra-mobile PCs, and consumer applications, addressing design requirements of density, speed, and power.

“We are pleased to see member companies introduce next-generation technologies that fully support the LPDDR2 industry specification. It is this type of advanced industry adoption that helps to establish high quality and reliability benchmarks required for low power and embedded system memory design,” said Roger Isaac, chair for the JEDEC JC-42.6 Low Power Memory Committee. “Denali is an active committee participant, working closely with memory vendors like Spansion to provide valuable recommendations toward the development of the specification.”

Denali’s LPDDR2 memory controller and PHY will support the full specification when released by JEDEC. LPDDR2 addresses the needs of mobile and consumer systems where the “PC memory” devices, DDR2 and DDR3, are unsuitable, as LPDDR2 offers a low power, low voltage, low pin-count memory in a range of densities and speeds that are closely matched to the needs of those mobile and consumer systems. In addition, LPDDR2 was designed to allow sharing of SDRAM and NVM memory on the same bus, which is extremely difficult in PC memory technologies. For immediate availability of a C-model, in advance of the silicon IP for Denali’s Databahn LPDDR2 memory controller and PHY, contact sales@denali.com.

“Many of our customers are looking for ways to upgrade to new controller technologies and are faced with several challenges,” states Marc Greenberg, director of Technical Marketing for Databahn products at Denali Software. “Many of the LPDDR2 features are derived from the best features of the LPDDR1, DDR2 and DDR3 technologies that we already support. This gives Denali an accelerated position to support the LPDDR2 architecture and continue to provide our customers with high-quality, interoperable, and configurable IP solutions.”

About Databahn Solutions
Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, and LP-DDR devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification test bench, static timing analysis (STA) scripts, programmable register settings, documentation, I/O pads and packaging. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/dram.

About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

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Denali and Denali Software are registered trademarks of Denali Software, Inc. Databahn is a trademark of Denali Software, Inc. All other trademarks are of their respective owners.

New Methodology Speeds Hardware and Software Design and IP Reusability

SUNNYVALE, Calif., June 26, 2008 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced it has licensed its Blueprint™ product to Cypress Semiconductor Corp. (NYSE: CY), for use in developing their PSoC® devices. Cypress’ hardware and software designers have deployed SystemRDL as a single source for register descriptions and are leveraging the Blueprint Compiler’s extensive generators to create and automate a variety of register views used in their development process. This single-source automated synchronization results in pre-silicon validation, architectural quality, and an increase in productivity.

“Today’s design teams are looking for methods to manage changes between the chip specifications and all the implementations used throughout the design and verification process,” states Jennifer Sirrine, senior design engineering manager at Cypress Semiconductor. “Our engineering teams wanted a single source for control register descriptions, and by using the industry-standard SystemRDL and Blueprint, have realized reduced integration time enabling us to meet our design requirements. Denali’s Blueprint provides Cypress with an integral and reliable platform solution for SoC design.”

Cypress PSoC devices employ a highly configurable system-on-chip architecture for embedded control design, offering a flash-based equivalent of a field-programmable ASIC without lead-time or NRE penalties. PSoC devices integrate configurable analog and digital circuits, controlled by an on-chip microcontroller, providing both enhanced design revision capability and component count savings. They include up to 32 Kbytes of Flash memory, 2 Kbytes of SRAM, an 8x8 multiplier with 32-bit accumulator, power and sleep monitoring circuits, and hardware I2C communications. For more of PSoC information, visit: www.cypress.com.

“Denali understands the challenges facing design teams today. The control register content has exploded in modern SoC’s with numbers of control registers often exceeding 10,000 instances,” states Sean Smith, director of Field Applications and product manager for Blueprint at Denali Software. “Our customers, such as Cypress, can utilize SystemRDL to specify all the control register content and act as a single source of information, and then with Blueprint Compiler, generate all control registers and related content such as documentation, RTL implementations, and verification test cases. Due to this automated synchronization, Blueprint results in increased chip design productivity and speeds IP reuse.”

About Denali Blueprint
Denali Blueprint, now part of PureView™ and MMAV™ 2008, is a SystemRDL compiler that enables a system-level approach to automating specification, view generation, and management of control registers for IP and SoC design. Blueprint will generate necessary outputs and views for design, verification, documentation, software development, post silicon debug and even enables early software development with SystemC™ Transaction Level Models. Blueprint guarantees interoperability with other EDA tools by inputting and outputting IP-XACT and SystemRDL formats. For more information about Blueprint and its architectural benefits, visit: www.denali.com/blueprint.

About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

Sole Provider of Memory Controller and Hard PHY Solution to Support Both DDR3 Chips and Modules for Networking, Storage, and Personal Computing

SUNNYVALE, Calif., May 29, 2008 — Denali, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced the immediate availability of its Databahn™ DRAM memory controller and hard PHY IP with full DDR3 dual in-line memory module (DIMM) support designed for bulk-memory and caching applications, including networking, storage and personal computing. Denali announced embedded systems support for discrete DDR3 DRAM chips last year as memory vendors began offering new devices to support data rates up to 1600Mbit/s per pin. This new DDR3 DIMM offering adds unique capabilities in the memory controller and PHY IP that are needed for networking, storage and personal computing systems using DDR3 modules at data rates up to 12.8GBytes/s per DIMM.

“The DDR3 DIMM is a high-volume product used by SoC customers who require a large amount of high-bandwidth memory,” remarked Brian Gardner, vice president of IP products at Denali Software. “To achieve this higher bandwidth, DDR3 DIMMs utilize a “fly-by” architecture which requires read and write leveling and gate training capabilities to be directly implemented and managed in both the DRAM controller and the PHY. Our customers look to Denali to provide high-quality, interoperable, and configurable IP that supports the DDR3 DRAM architecture where DIMM concepts can be applied.”

About Databahn Solutions

Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, and LP-DDR devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification test bench, static timing analysis (STA) scripts, programmable register settings, documentation, I/O pads and packaging. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/dram.

About Denali Software

Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions and platforms for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products, and services is available at www.denali.com.

New Models for Latest Memory Technologies Plus Advanced Features and Support for Standard Protocols Increases Productivity and Minimizes Design Risks

SUNNYVALE, Calif., May 22, 2008 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced the availability of the new MMAV 2008 packaging, the most widely-used memory verification IP product. Denali's MMAV has become an industry-standard solution for verifying memory interfaces and ensuring system correctness. This latest package release provides a complete and an accurate solution for simulating memories, including support for most of the memory technologies, including DRAM, SRAM, Flash, and Card memories, and several standard protocols. Verification engineers can utilize MMAV memory verification IP early on in their design cycles, minimizing the risks of non-compliance and ensuring chip success.

"Denali continues to strive to deliver the highest-quality of simulation models for cutting-edge memory technologies," remarks Sanjiv Kumar, manager, Verification Products at Denali Software. "Our tens of thousands of pre-verified memory models support various parts from all major memory vendors and deliver the best quality and reliability needed for our customers' system memory requirements. The advanced MMAV architecture allows seamless integration with different verification methodologies like eRM, VMM, OVM, etc."

MMAV 2008 can be utilized for cutting-edge memory technologies and provides new simulation models for mobile DDR (LPDDR), mobile DDR2, ONFi, GDDR4/5, eSD, eMMC and also for SystemRDL, DFI, AMBA (AXI, APB, AHB), and OCP protocols. Additional new advanced features found in MMAV 2008 includes transaction callback, assertions report generation, and error configurability. PureView, a supporting MMAV product, incorporates Blueprint Compiler technology, which generates necessary outputs and views for design, verification, documentation, software development, post silicon debug and even enables early software development with SystemC™ Transaction Level models. For an overview on MMAV 2008 and its new advanced verification techniques, stop by to speak to our experts at the Denali booth (#1611) at the Design Automation Conference (DAC) in Anaheim, CA., during June 9-12, or register now for an in-depth presentation and hands-on tutorial, "Increase Your Productivity with High Quality Memory Verification IP," at MemCon San Jose, on Monday, July 21, 2008.

About MMAV

Denali's MMAV product is the industry's de-facto standard solution for modeling and simulating memory during functional verification. MMAV has been used in thousands of designs to ensure correct and optimal behavior and timing between the system design and off-chip memory devices. MMAV utilizes a powerful and effective approach to modeling memory. MMAV 2008 is available immediately. Additional MMAV 2008 information and an evaluation can be requested at: http://www.denali.com/mmav.

About Denali Software

Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions and platforms for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products, and services is available at www.denali.com.

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Denali and Denali Software are registered trademarks of Denali Software, Inc. MMAV and Blueprint are trademarks of Denali Software, Inc. All other trademarks are of their respective owners.

Widely-Used DDR Memory System Specification Takes Advantage of DDR3 Performance and Minimizes Design and Integration Costs

SUNNYVALE, Calif., May 21, 2008 – Denali Software, Inc., today, as one of the DDR PHY Interface (DFI) specification participating members including ARM, Denali, Intel, and Samsung, announced the release of the new DFI specification version 2.0. The collaborative technical working group, which includes representatives from these companies, delivered several improvements and enhancements in this latest version of the DFI specification. This version of the specification extends support to include DDR1, DDR2, Mobile, and DDR3 memory; adds read, write, and gate training interfaces; and improves upon the interoperability features between the memory controller and a DDR PHY. Chip architects, memory controller vendors, and PHY providers can utilize the new specification to speed their DDR memory system design and integration, and reduces the significant verification costs.

“DDR3 created some technical challenges for this industry collaboration. The team rose to the task, and the result is a specification that ensures interoperability and high performance,” said Brian Gardner, vice president of IP products at Denali.

The DFI specification 2.0 is available through a click-thru license at: www.ddr-phy.org. The official version of the specification has been based on the 1.0 foundation of the common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs. This specification allows designers a standard that has wide industry acceptance and ensures that the controller and PHY will work optimally together and no changes will be required to the hardened logic, resulting in reduced cost, time-to-market, and increasing reusable system IP.

“As many designers are migrating from DDR2 to DDR3 technologies to take advantage of the performance, this places a massive load on the controllers and increases the importance of a standard interface between the controller and PHY,” said Bryan Jones, Corporate External IP Management, Mobility Group for Intel Corporation. “The contributions from the technical team help to increase momentum and opportunities, and we look forward to furthering the usage of this specification within the industry.”

About the DFI Specification
The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, visit: www.ddr-phy.org.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions and platforms for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products, and services is available at www.denali.com.

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