LP DRAM Market Status & Market Drivers to Date: The basic concepts and feature set for the Low Power DRAM roadmap were set down nearly ten years ago, and had the following basic requirements: (1) The LP DRAM roadmap would lag the ‘PC DRAM’ (mainstream DRAM) roadmap by about one architecture (i.e. three years), and LP DRAMs would have several required features: (a) Temperature Compensated Self-Refresh (TCSR); (b) Partial Array Self Refresh (PASR), (c) advance the voltage reduction one level past the PC DRAMs, e.g. when PC DRAM went to 2.5V with DDR1, LP DDR DRAMs would go down to 1.8V; when DDR2 went to 1.8V, LP DDR2 DRAMs would be 1.5V; etc., and (d) LP DRAMs would have a well defined Deep Power Down Mode...turning off power altogether.

In an industry known for not being able to see more than a month in advance in terms of market trends, twists and turns, much less forecasting the technical tools to implement any plan, this was a bold, and for the most part, successful bit of insight and challenge. In that era, cell phones were a nascent 160MU/year market, and have now been running at more than a 1.0B to 1.2B units/year clip for 3-4 years.

Mobility, and its attendant demand for long battery life, undiminished performance and features, has been THE MegaTrend in chips for the past decade or more, taking over from the 1980’s-led PC era of WinTel, which, though PCs are still the largest revenue market for chips, has been reduced to ‘normal market evolution’ today. Everyone got their PC years ago, and though almost everyone also has a cell phone today. But phones are evolving more rapidly than PCs, adding features, and driving technologies. So drawing a line in the sand, and staking out a technology direction for Low Power DRAMs, so long ago, was timely, much needed, and beneficial, and has served its purposes remarkably well.
This roadmap served the industry well through Low power SDR DRAMs (running concurrently with the use of DDR1 in the mainstream PC space), and Low power DDR1s when the PC space was using DDR2, etc. But for a long time Low power DDR1s had a hard time hitting the fastest speed bin…LP DDR1-400, and a half step, to -366, was proposed, accepted and became a standard for a time. Even today, the LP DDR1-400 spec is not well supported, even as Low power DDR2s emerge. The prospective “three year” time lag behind the PC DRAMs, has also started to look a little ragged in terms of product availability and take-up in the market, as well as (increasingly and emphatically), hitting required performance levels.

Below we have ‘borrowed’ and adapted a chart presented by Elpida at Denali MemCon Japan late last year, showing the estimated market mix of LP DRAMs by various competing architectures In a nutshell, LP DDR1 is in the process of replacing LP SDR DRAMs, and LP DDR2 is “not here yet.”, but is expected to gain traction within two years. Other presenters suggested that nearly ALL LP DRAMs today were used in cell phones and PDAs, though in phones, they share RAM honors with SRAMs and PSRAMs, but of which are in steady decline today as LP DDR1 DRAMs ramp forward.

Source: Elpida at MemCon Japan, 2007; Denali

LP DRAM New Challenges, New Markets, New Tools: But life does not stand still, technology does not always give way as we foresaw years earlier. Once the industry engaged in the task of driving down power in DRAMs, it saw many alternative paths to take… as well to respond to a diversity of applications requirements and device LP enablement methods. And staying on the original roadmap, which necessarily had many “TBDs” on it in terms of “how we expect to achieve this and that”, has not always been as easy or as possible as anticipated.

Today, lower power solutions are being sought in new circuit designs, improved process flows and chip designs, in simple changes in layout (as from x32 to x64 designs), and in borrowing the lessons of other ‘roadmaps’ and products. Unexpected problems are being encountered (the difficulty in reaching high data rates), and the shifting sands and demands of new markets are making it harder for ‘one-size-fits-all’ solutions. LP DRAMs, to date largely confined to cell phones and PDAs, are chomping at the bit to get designed into mobile computers of various sizes.

Today, there are NO Low Power DRAMs at all in the formal laptop segment, which market constitutes the largest GB/year market for ‘mobility memory’: 125M Units x 1.7GB/system easily trumps 1.2M phones with 32-64MB/system, as even flash is making a serious run for the LP memory role in phones daily.

In short, the Low Power DRAM roadmap is running into problems, even as attractive LP features are being picked up in more traditional DRAM products. Also, the hard lines separating one class of products, and differentiating them from one another, are blurring. In fact, I believe that not only will the Low Power DDR2 DRAM of 2012 will look far different from what we see launched today, but there will be a variety of prospective LP solutions for the similarly bewildering array of power requirements of the industry. “Power reduction” interest is pervasive throughout the industry today, and though the LP DRAM roadmap can serve many or most of those interests, many applications are likewise finding their own ways to keep power down, inside or outside the confines of the LP DRAM roadmap.

“DRAMs” or “Memory” is only a part of the system power problem, and only a part of the solution which system architects face today. To see this, look no further than Intel, which has launched in the past 3-4 years, major ‘back to the bare metal’ redesign initiatives aimed at power reduction in their MPUs, with some major business successes resulting (forty years on, I never cease to be amazed at Intel’s successful technology initiatives): Banais led to their Centrino product line, and their most recent initiative led to their Atom processor for the Ultra Mobility Sector…already sold out, over-subscribed, over-designed-in and a certain money-maker and market success for Intel.

LP DDR2 DRAMs offer a solution: Despite the shortcoming-to-date of the most recent LP DRAM product initiatives, there is a strong motivation and interest in getting the LP DRAM back on track. A task force within JEDEC is in the final stages of creating a spec and many vendors will have LP DDR2 DRAMs, up to -800 versions, by the end of 2008..much higher performance and much lower power than even the best of the LP DDR1 DRAMs now avialable…twice as good on both counts is a reasonable expectation: namely, twice the datarate at half the power. This work is being driven largely by phone makers and, of course, supported by the technology roadmaps of LP DRAM vendors. There is also associated work to support server DRAMs with lower power versions (formalizing the steps, and voltage step-down steps, already taken by Qimonda and Micron)

Can LP DDR2 DRAMs give the industry what it needs for next-generation, high-performance low power systems? Can it regain the momentum the LP DRAM roadmap needs, to satisfy a large fraction of the industry’s low-power memory needs? Or are the needs too diverse and the timetable too uncertain, that users will not be able to wait for Golden LP DRAMs to appear at reasonable prices?

Examples of what activity is going on in this area today include:

Server DRAMs: Qimonda and Micron’s 1.5V DDR2, taking the generation-to-generation voltage step-down one step further (or viewed another way, applying the LP DRAM voltage spec to what is otherwise a PC DRAM.) Since some DRAM applications do not need the speeds available in traditional (Standard) DRAMs, vendors find that they can get enough speed and lower power just by dropping the voltage; As it has been the case for some time, the speed distribution of DRAMs manufactured is much faster than what the market needs; there is no price premium for DDR2-800 over DDR2-667, just as DDR1-400 cost about the same as DDR1-333. Vendor cost reduce to improve their finances, the speed comes about for free. So why not take a different tack, and make a lower-voltage, lower-power, sufficient-performance DRAM family?

Start-ups aiming at LP RAM technologies and markets: NanoAmp (now a part of AMI) and ZMOS ‘back to first principles’ RAM roadmaps (recall that SRAMs were the SOLE RAM for all the watch and calculators in the 1970s and 1980s, and were used in early generations of PDAs even in the late 1990s.) These two companies were launched and built on the emerging need to take an original look at the needs of the LP market and not be constrained by ‘what other people, or the industry groups, were doing.” NanoAmp is SRAM focused; ZMOS uses advanced circuitry they developed to drive power down in DRAMs.

Back to “Cleverness”: All LP DRAM makers are very clever in the ways in which they can drive a few microamps of power out of their DRAM and SRAM designs. From what’ been seen so far, Elpida is one of the best, and is seen as a major LP RAM innovator. They launched an “ECC-enabled” Low power DDR1, which reduced refresh rates and, therefore, refresh currents, and then corrected out bits which were dropped. Hynix has followed with a similar solution.

Elpida also announced a x64 LP DRAM, which give the user the bandwidth without have to move to higher frequency, which seems to be the cause of most LP DRAM performance limitations today. Achiecing high bandwidth with wide buses, not fast clocks is an important LP memory and system design tool.

Jumping the tracks: LP features jumping out of the LP Channel into the mainstream: The industry standard DDR3 DRAMs have adopted, as an option, the PASR and TCSR features which were mainstays of the original LP DRAM roadmap. LP becomes mainstream and not nichy…but not for everyone, either.

Qimonda, in its new and agressive DRAM roadmap, extols the LP virtues of its Buried Word Line architecture (not to mention its small DRAM cell size.)

Source: Qimonda

Dense SRAMs are also resurgent in taking on the LP RAM marketplace, esp. for lower densities which may not be well served, if at all, by LP DRAMs…64M and even 128M, with higher datarates than SDR DRAMs are capable of. Renesas now offers 64Mb SRAM with 55ns access times and low power; lithography already successfully employed in DRAMs would suggest that higher densities of LP SRAM are achievable in the near future, curing some deficiencies in the industry’s low density “DRAM” support.

Embedded DRAM Potential for Super LP Systems: Another possibility that is coming into focus for some applications is that old whipping boy of memories that refuses to go away. It is the embedded DRAM, or eDRAM, which is said to be present in more than half of ASIC designs in 65nm and finer design rules. At 65nm, which is available from most ASIC vendors with eDRAM (IBM, NEC, Toshiba, Samsung, TSMC), the user can embed 250-300Mb of DRAM…which is in a part of the LP market space which is ill-served by existing standalone DRAMs, either SDR, DDR1 or DDR2…the lower densities needed only for applications that require an LP RAM as something of a ‘system cache’, and not as a ‘mainstore’ of significant size. Once 45nm is up and running...and it is ramping today…the available eDRAM densities will be greater still. Certainly, 64MB of eDRAM is within reach.

Embedding the DRAM into the ASIC/SoC, increases user options and gets around some of the performance limitations of standalone memories: One can design in a 256-, 512-, or 1024-bit bus and turn the clock down low, reducing overall system current. The high currents required to move data off the chip to the MPU-host is also reduced significantly. Since it is system power that is usually the issue, and the memory is toggled into its LP mode by external commands, this places the (e)DRAM right inside the ASIC, which can improve memory power management by the host, and perhaps make possible more “LP Modes” and “LP Methods”.

As most eDRAMs were originally optimized to replace very fast SRAMs in on-chip caches, rather than low power, this constitutes a new (or resurgent) direction for eDRAMs, which is totally in line with what most foundries now have in the process flow: a high-performance process flow and a Low power process flow.

The vast majority of cell phones today moving towards using LP DRAMs of 256Mb density, so eDRAM should be an option, based on that fact alone.

Double Down Voltage options: Some vendors are looking at a double reduction in voltage…using 1.2V for LP DDR2 instead of 1.5V, finding that they either can hit the speed with lower voltage, or that lower power is more important in their applications than the higher speeds. (This is another issue…the relative importance in applications of performance v. power…some need one more than the other, which is not to say, there is an emerging class of applications which need lots of both.

This Low-Voltage with LP Features trend is both new and sometimes confusing to users. For reference, here are the I/O Volatage standrads for the several DRAM roadmaps in place today.

a: Low power DRAMs (LP DRAMs) all have (1) TCSR, (2) PASR, (3) advance voltage
reduction one more step compared to PC DRAMs, (4) Deep power down mode

b: Low Voltage DRAMs have voltage stepped down one increment from PC DRAMs,
but are otherwise functionally the same

*: This recent standards decision to double down the LP DDR2 voltage, to 1.2V
instead of 1.5V, was a departure from the earlier LP DRAM roadmap, in order
to get further power savings, without compromising performance for most applications

For most voltage standards, datasheet tolerances are "+/- 10%"

Many or most products also use several voltage domains on their chips

We do not have a lot of high expectations that this chart will remain stable for too long, or will encompass the totality of Low power DRAM offerings; once 1/2V is mastered, why not offer a 1.0V or 0.9V specialty part (or one that has a user-selectable 1.0V 'option')? Do the benefits in 'LP' or 'performance' of using a x64 chip justify its off-roadmap character? Which applications cannot get enough LP from a 512M, x32 LP DDR2, or not enough performance, that they need to (and can cost-justify) a specialty LP DRAM? In some ways, this question looks much like that faced every few years with the graphics markets.

Summary and “Market Direction”: We have little doubt, today, that LP DDR2 DRAMs will make a very strong appearance by the end of 2008; there is too much inertia, interest, and the stakes are too high for it not to happen. But it will be difficult to get fully-compatible multi-sourcing among vendors, and exact-spec commonality. The nature of the market demands and succeed on competition in secondary parameters, and metrics. So, despite "JEDEC" LP DDR2 DRAMs being THE high volume roller for servicing the LP DRAM market in 2010, diverse applications and requirements will combine with diverse LP chip design methodologies to make a fragmented “LP DRAM” market that will defy efforts to keep within the channels of some finite set of features, standards and conventions.

Somewhere along the line, the small and maximum-portable end of the PC segment needs to get an LP DRAM roadmap of its own, optimizing its performance and power requirements, even as it has avoided the traditional LP DRAM roadmap so far.