Though Financially Challenged, Memory “Industry” Continues to Run Flat Out, Close to the Edge, and Very Efficiently

That the memory industry is in dire straits is undeniable. Among memory makers, only Samsung appears to be profitable in 2Q08, though certain product lines here and there, from various vendors, may also have their heads above water. Indeed, 2Q was not much different from 1Q from a financial viewpoint, and 3Q, now half done, will further erode the financial positions of all memory makers.

DRAM makers suffered horrendous losses, and the more positioned they were/are in PC DRAMs, the more they lost, despite some remarkable improvements in costs of production. Demand remains strong, and a few datapoints indicate that in terms of GB shipment growth, 2Q08 is about 60-70% more than 2Q07 for DRAMs, and up more than 150% for NAND flash. These are both very good growth rates, judged by the standards of recent DRAM and NAND history, though not as good as we witnessed in 2007 compared to 2006. Some economic hesitancy and a tightening of China imports in advance of the Olympics appear to have dampened demand from what it would otherwise be.

Demand is strong, but both DRAM and NAND supplies, borne of large CapEx in 2006-07 and major productivity improvements, is stronger. Downward price pressure has been nearly unrelenting in 2008, and for most of 2007, as well.

But consider these observations, too, which may tell us something about what the ‘Industry re-balance trajectory’ might look like down the road:

• The industry has made major strides in cost reduction over the past 18-24 months, moving from 8F2 90nm to 70nm and better in DRAMs, with some 6F2 cells, and 60nm+ to 45-50nm in NAND flash, while pretty much completing the SLC to 2-bit MLC transition.

• “Operations” has been cleaned up with closure and repurposing of 200mm lines, R&D streamlining, additional technology sharing (JVs and partnerships); Expenses have been sharply curtailed at most DRAM and NAND flash makers.

• The DRAM industry has jumped from 512M to 1Gb as the DRAM of choice, with the 1Gb share of the mix being about 6% of bits in June’07 and 65% in June ’08. Most bits are in 1Gb chips today, as across-the-board 70nm processes have become firmly established and high-yielding. 1Gb chips first exceeded half of DRAM shipments only in March of this year. Next-generation 5Xnm processes, with additional 6F2 cells, are headed for 2009 launch and ramp.

• Planned CapEx, esp. for DRAM makers, has been cutback, after binging for more than two years. These are not just strategic cutbacks, to avoid sending additional oversupply to the market; these are sometimes dictated by cash flow problems because DRAM prices are so low, and have been for so long (same for NOR; cash flow is hurting both Numonyx and Spansion’s ability to move to the optimum process and wafer size position). Many DRAM makers felt pain as long ago as 1Q07, so it has been brutal and long; indeed, one cannot spend what one does not have. To make matters worse, credit is tightened up on loans, and no one will offer more stock at today’s sub-book valuations. Memory makers are in a tough situation; many could not prudently add capacity if they wanted to, given the market outlook, prices and their own cash flow situation.

• With abandonment of less productive 200mm lines, and taking in occasional foundry business among DRAM makers of existing fabs capacity, the Industry-wide capital stock being applied to DRAMs and NAND flash is leaking, as well as growing due to CapEx additions; releasing the non-competitive capacity while adding first rate capacity on the front end. DRAM and NAND flash makers make much of the proportion of their wafer starts that are being run on 300mm lines, so strong an economic case can be made for them compared to older 200mm wafers.

Running Flat Out Leaves Little Room to Respond to a 'Crisis' or 'Upside': All these actions have led to a situation where the DRAM business is operating at, or close to, its maximum level of efficiency. There is increasingly no room for failures, missteps, uneconomic factories and back-generation designs; across every enterprise, all the less-economic factories are being redirected or disabled. Hynix’s fab in Eugene, OR is only the latest and most visible example. There may have been no other time, when so much of the industry’s DRAM (and NAND) capacity was so close to the leading edge technology envelope…with its nose right up against the glass, gasping for air. With tight or negative profit margins, the option of concurrently running designs at several different process nodes, even when some are less than cutting edge, is vanished or sharply reduced.

Downturns always weed out non-competitive capacity, but this time it is in the extreme; for memory makers, who have consistently been driving the industry in pushing processes, this one the most unforgiving ever.

What this situation may expose, however, is a potential vulnerability. If demand responds even more strongly to new applications opportunities presented by these $2.10 1Gb DDR2-800s and -1066s, or if DDR3 take-up accelerates, or under-$2/GB NAND Flash, or DRAM vendors cannot move to the next generation 6F2 cells and 5Xnm processes. A significant DRAM demand upside, or even a continuation of the current demand expansion rate, for more than a few more quarters, could push the industry past its ‘response limits’ and create a sharp change from today’s supply excess environment.

On the NAND side, the move from SLC to 2MLC is nearly exhausted as a means of easily growing GB shipments, and x3 (three bit MLC) will make scant contribution to net GB growth in 2008. The next 12 months will be spent converting and ramping 4Xnm designs before launching sub-40nm and x3 designs in 1H09. Most bit growth for NAND in 2008, about 2/3 of it by our calculations, will come from more wafer starts, with most of the remainder coming from process shrinks now underway; additional wafer starts are on the way, to be sure, but cannot be turned on a dime, either, in the event of a sharp and sustained increase in demand.

Out further, DRAM and NAND Flash market drivers and market make-up, have great uncertainties. In 2007, DRAMs grew at an unexpected 90% Y/Y growth rate and 2008 looks like +60-70%; NAND's more than doubling in output every year needs huge new markets to develop to take away planned output increases. The slowness of the SSD market to gain traction, recognized as the 'Next Big NAND Demand Driver', was certainly an important factor in NAND price weakness in the past 12 months. At its present growth rate, the market needs several of these huge markets to develop in the next few years, to absorb NAND output already on the drawing boards. The market needs wholly-new application classes in the manner that the Apple's iPod was in the fall of 2005...calming the market critics, ex-post justifying the billions of dollars spent on NAND Flash fabs, giving hope to NAND makers that prices will come up and up.

MemCon 2008-- The Issues: Continuing our top level discussion of the 2008 Denali MemCon event below, we will be discussing a few of the important issues that were surfaced during the three day event. This industry is not slowing down a bit, and just when one gets comfortable that they can see down the road for a while, something changes, some significant issues emerge, some expectation disappoints, some external force or constraint changes in an unforeseen way, that forces an industry-wide review and resetting of strategies, technical directions, business models…and today, survival strategies. Poor profits for more than a year now, amid increasing demand for new and innovative products (i.e., more R&D), and for facility expansions (the market is still VERY strong, in GB and Units), have pushed some companies to retreat, be spun out, and/or to seek partnerships that enable them to go forward.

Here are some highlights of important issues that were developed at this year’s MemCon:

The Issues: Spoken in many ways and from different perspectives, there was a broad consensus that (1) the movement to a NAND Flash centric and driven industry was Big News with Big Consequences, (2) The consumer end markets were vastly different from the historical Major Chip Industry Force of the PC-compute space, and (3) we are just at the beginning of these transitions. As grim as the P&L looks today for almost all memory makers, demand in terms of silicon and units of end systems, is robust, volatile and rapidly changing. Opportunities, challenges, and pitfalls are everywhere.

Defining the Needs: There are major “market and product characterization” uncertainties ahead, as was evident in the presentations and analysis of end markets. Applications requirements, in terms of endurance needed, read and write performance and use of MLC, SLC, x3 (or x4) are often still up in the air. For DRAMs the uncertainties are about the need and speed of using DDR3 DRAMs, to replace DDR2-667s which have been the PC mainstay for more than two full years. In the mobile space, how much “LP” is needed is not clear and IS variable from system to system. In the end markets, the precise definition and needs of the variety of low-end ‘computers’ on the system side is still fuzzy and very much a moving target.

Fate of NOR?, or Fate of NOR! Numonyx and Spansion are now free agents; Spansion for about 18 months and Numonyx only since it was spun out from Intel and ST and the end of 1Q08. Both have formidable technology portfolios, both are racing against a NOR flash market which faces both slow growth and often a full court press from NAND, both are trying to find new applications and products while cost reducing aggressively and holding off competition in the biggest NOR market: cell phones. This they are doing all at once, plus competing with each other for market presence and design wins in the next and next-next cell phones.

In seeking new and different places to apply their technology, Spansion’s recent EcoRAM announcement seeks to displace DRAMs based on the EcoRAM’s lower power Data Servers, was joined in this meeting with a new-Numonyx likewise “new NOR Direction” market development. Numonyx announced in a press release at MemCon their “Velocity LP DDR NV RAM” product offering. Never very specific about what exactly it was, we presume it is a multi-chip-in-single-package device with NOR flash and LP DDR DRAM, in a tuned and optimized code-executable front end for the larger cell phone memory stack, backed up with lower-cost NAND flash.

Fear and Loathing at the Low end…no, “of” the low end: It is not just at MemCon that the concern and interest over how the ultra-low end of the PC market will develop is palpable. Expected to ship perhaps 10M units in 2008, depending on what definition is used, the Ultra Low Cost (ULCPC), Ultra Mobile (UMPC), MID (Mobile Internet Devices), Net Computers, or the “Pocket PC”, this class of machines is, at once, beholden to little in the establishment architectures and methods of implementation: Windows and Vista? Well, maybe Linux? HDD? No, SSDs seem quite enough. AMD or Intel MPU? Well, maybe, or maybe Via or maybe ARM.

Unhooking from the ‘tradition' means freedom of architecture and implementation, as well, of course, freedom from having to pay for those high gross margins of the established suppliers. RAM amounts and screen size are reduced; power is down sharply (paying homage to the spiraling out of sight power bills), and battery life extended. The driving force is small form-factor and even smaller cost and price; where one’s laptop (notebook) might formerly have been used in the field and then ported and synched up to one’s desktop in the office three to five years ago, the industry is moving one rung down the ladder: desktops are now become laptops (portables), and the ULPC (or PDA, SuperPhone) is taken on the road and synched up when in the office. The industry consequences of this movement could be grand or devastating, depending on whether one is “Wintel-Dell-HP”-aligned and will suffer loss or cannibalization of their larger system and higher margin business, or one of the Asian PC minions eating the bottom of the market like piranhas. (Not too different from the US carmakers’ “SUV profit” threat felt from hybrids’ small form factor, high gas mileage “Mini Coopers”, and smaller profit potential.)

While there were NO dedicated presentations aimed at this particular major system trend, it rippled through many conversations and presentations.

Focus on Memory in Phones: The cell phone memory stack is a major locus of churn, diversity, uncertainty and change. Many of the speakers crossed this issue in their presentations. Standards are only loosely present, the 1.2B annual shipments of phones not only span ‘NOR+PSRAM Ultimate Simplicity’, to the high end that is truly a small ‘Mobile Electronic Office’, with Internet, near-TV, calendaring and messaging, complete A-V capability… as well as a full keyboard. Across the spectrum, NOR and NAND, PSRAM and LP DRAM, are mixed and matched to the application…and are showing little interest in becoming less diverse or consolidating into a few broad classes. Constant pressure to increase phone features within a limited power envelope and simultaneously reduce chip-count are always frustrated by technical trends to more MB/system and higher performance and a BOM cap. Most phones still have Flash + (PSRAM or DRAM) on the inside, and increasingly support an external NAND Flash insertion slot on the outside.

Denali Keynote: In the clearest statement to date about Denali’s focus and corporate contribution to the industry, Denali’s co-founder and CTO, Mark Gogolewski discussed the broad subject of product enablement, and the art, and science (and discipline and the industry’s compelling needs) of getting new silicon capabilities launched into the market. As the world shifts from a more predictable PC and PC- DRAM centric growth trajectory to one dominated by rapid product turnover, an increased willingness to pioneer new systems and technologies and ‘make markets’ in the consumer space, the need for a powerful and capable group of infrastructure enablers is increasingly necessary to pave the way, remove barriers and obstacles to rapid execution and implementation. Denali’s business is largely been built around such enablement, with critical IP and expertise, memory market and technology domain knowledge, significant ASIC and SoC verification capabilities, and system interface optimization tools, making themselves an essential partner to system houses and SOC designers to insert those custom chips and systems into the marketplace.

See the Denali MemCon website at for the complete proceedings, available on line in just a few days.

Denali hosted another successful MemCon event on July 21-24 in Santa Clara, CA, with topics devoted solely to Memory and Storage. The show featured 28 speakers, three panels and a full-day of tutorials on each of Denali’s products, which took place July 21.

More than a dozen companies sponsored the event, which is unique in its ability to draw together a large audience of ASIC and SoC designers to hear talks about memory company strategies, product roadmaps, and other related topics, and to understand several contentious industry issues. MemCon is viewed as a unique opportunity to present one’s company perspectives and strategies, ‘opinions,’ expertise, and product direction to potential and existing customers. It offers an opportunity to tell one’s story to a large audience of dedicated chip designers and system architects who have a vital interest in knowing what is going on in the memory business, from a technology and markets viewpoint.

The lead Platinum Sponsorship group included Rambus, Qimonda, and Spansion, followed-up by Gold Sponsors that included Intel, Numonyx, SanDisk, and Samsung, and then backed up by an additional confab of sponsors anxious to tell their stories and show their wares.

The MemCon Agenda can be found at: www.denali.com/memcon

The complete presentation materials, by individual presenters and panelists, are headed to the Denali website, too, but will take a few more days to appear. Some presentations were recorded, as well, and can be replayed with the audio accompaniment. For the full presentation materials, please check back later during the week ending August 8 at the MemCon website.

In the paragraphs below, we’ll be discussing a few of the major aspects of today’s chip and end system industry status. In a follow-on piece, we’ll bore in and focus on a few of the important issues, uncertainties and rapidly developing themes which were brought to the forefront at this year’s MemCon.

Timing is Everything, Right? Despite today being a very rough time for memory makers (MemCon kicked off right in the middle of the reporting of 2Q08 earnings results, which were very grim, indeed), the are many trends-in-motion clear and murky, which are transforming the industry in ways not seen in decades: shifts in driving forces and applications, new business models for memory makers, huge progress in cost reduction in the past 18 months and promises of more in the next 24 months, technology forks-in-the-road…which seem to be occurring at a pace that is stronger than ever before, despite the industry having passed the forty year mark since its inception in the late 1960s. It is not tiring, it is not slowing down…but, it is not forgiving, either. The vice of change in 2008 is pressing vendors as tight as anything that has gone before.

Trends, Changes and Possibilities

The Industry: The industry status in the middle of 2008 is uncertain due to the larger economic outlook and technical directions in key markets, but still quite strong in terms of unit demand for increasing chip functionality. But, the industry is severely weighed down by a large pocket of oversupply and the attendant price declines in the DRAM and NAND Flash markets, which together are about 15% of total semiconductor industry sales, but more than 2x that of industry Cap Exp and of its leading-edge capacity. These two markets alone are probably sufficient in influence, with their poor financial performance, to offset the entirely of the remaining industry’s 2008 profits. The memory makers are selling much more, but getting paid far less for it than last year (which itself was not all that good, either).

Demand is strong for end systems: Price weakness should not be confused with demand and market weakness. The two largest memory and chip end segments, PCs/computers and mobile phones, will BOTH show good unit growth in 2008 and both will absorb significantly more memory/unit than in 2007, in part due to increases in system features and incremented in response to 2008’s lower prices.

Opportunities Proliferate: Not surprisingly, given the sub-theme of the conference of "Mobility and Storage", many of the presentations focus on what is happening in the phone space. Many of the observations from differing industry vantage points crossed paths and/or concurred with one another, but there were large areas of looking at the elephant and seeing different attributes and trends. Harmony was hardly universal, especially when looking into the future.

NAND Outlook? The smartest money and most cogent argument seems to favor a slowing of the rate of price (cost) declines, and a gradual slowing of NAND GB growth over the next several years . The consequences of technical factors on the supply side that make cost improvements more difficult to achieve are not inconsistent with the shortage of clearly-defined and developable end markets, beyond that of SSDs (about which there is some vocal dissent, too), that can absorb such vast quantities of NAND Flash GB shipments as would be shipped under the “massive GB growth and 50% price down annually business as usual” scenarios. This is not surprising; NAND has grown at CAGR of more than 150% Y/Y in GB shipments for a decade and price-reduced more than 50%/year. Much of the easily-developed market and technology has already been harvested. But, it is hoped by all NAND players, that the existing price level for both NAND and DRAM will attract new system possibilities, and/or a recasting of established memory subsystems in PC/computers and mobile communicators.

Memory CapEx slowdown is welcome: Memory makers, due to ‘irrational exuberance’ in CapEx, combined with major productivity improvements in 2005-6-7, have created a large production capacity surplus, driving prices down and profits into oblivion. Fortunately, both the DRAM and NAND flash markets are still booming, with respective growth rates in GB/y shipments of about 60% and 150%+ for 2008, that, with prudent expansion going forward, these surpluses can be absorbed by a natural expansion of demand.

Hoist by Their Own Petard: Huge productivity improvements and reduction in cost, driven by technical advances DRAM and NAND are co-culprits of today’s market excesses. NAND Flash prices are said to have dropped 20% in JUNE (one month!), which caused many poor 2Q08 financials for major NAND players, but also some expected and welcome capital reductions, underlain by the thought that, perhaps, supply has got ahead of demand in this burgeoning market of markets. NAND prices came down more than 60% in the past 12 months and DRAMs dropped more than that; costs of manufacture for both have exceeded historical norms by a wide margin, but have not kept up.

Not satisfied with 2-bits per cell for NAND, which move is about saturated, and nominal 60nm processes, we’re now off and running with x3 (= 3 bits/cell) NAND and a widespread use of 4xnm processing. For DRAMs, 2007-into-2008 marked a breakthrough period when 70nm almost wholly displaced 80-90nm processes, and brought with it 1Gb DRAMs in place of 512Ms…rapidly and at lower prices. Advances in the elemental DRAM cell layouts have also contributed significantly to cost-of-manufacture reductions, with more to roll out as we move through 2008-09, and advanced designs move into volume production.

These advances have resulted not only in DRAM cost reductions but (not surprisingly) in significant output increases, given that the industry’s core ‘high-fixed cost’ economics make it imperative to keep each and every fab full, and there is little opportunity to swap DRAM or NAND Flash production for alternate products; historically, strong demand growth from end markets has been insufficient to absorb all the DRAM MB that are rolling out of fabs today, so that prices have continued to be hit hard. Recent spending cutbacks will be useful in slowing supply growth from its unsustainable levels, but have not gained real traction yet; red ink was abundant in 2Q08 and into the foreseeable future, along with perhaps some additional consolidations and shared resources ventures.

NAND Flash prices started seriously heading south in 4Q07, after a brief respite of rising and stable prices in 2Q-3Q07. The 'two quarters of price stability' last year, in turn, had followed a rapid price decline in 1Q07. But this year, the 1Q-2Q recovery was brief, April and May only, instead of the two full quarters of the 2007 bounce, which had restored prices fully to their YE 2006 levels. In 2008, NAND Flash prices have been mostly down and down...including 20% in June alone!

Some view this year's heavy and continuous price competition, which has driven the benchmark 8Gb devices from about $9.00 a year ago to $2.25 at the end of this past June, as being a result of weak demand. But shipment data, from WSTS, NAND Flash manufacturers who report their sequential and Y/Y GB sales and production growth in their quarterly financial calls, and a variety of other sources, indicates that suppliers have shipped about as many GB of NAND Flash in 1H08 as were shipped in all of 2007, indicating that the market is still growing at about +170% Y/Y growth rate, comparable to what we saw in 2007 (compared to 2006). Unfortunately, with the heavy price erosion, the NAND market in 2008 will be about the same size, in revenues, as it was in 2007: $15B, +/- 2B. However, one can see clearly the impact of pricing, if price declines ease much before year end 2008, the market COULD come in about $5B larger, or about $20B.

So when Samsung, Hynix, Micron, and SanDisk say they grew their NAND output by 30% from the quarter prior, that's a pretty impressive ramp, but it means they only picked up a small share of the industry's total output: 170% Y/Y is about 28% sequentially, Q/Q.

NAND suppliers have been hugely successful in adding output: So, if it's not weak demand, it must be strong supply, right? Yes, and therein lies the danger and difficulty in riding the NAND wave. This difficulty exists for the handful of players who are investing $3B per megafab, a few years in advance of its peak output; who see looming large (potential) NAND markets, such as SSDs; who recognize that to play in '10, you have to put the shovel in the ground today; who recognize that much of the demand in say, 2012, is truly speculative, based on some new applications and some natural price elasticity to expand shipments into existing markets of iPods, iPhones, USB drives, and DSC cards.

There is no credible way of determining what the average flash card GB will be is 2012, except by trend extrapolation. Who would ever guess that people want more photos in their personal computer than there are books in the Library of Congress, or 10,000 songs on their iPod, or more GB on their computer than were on a mainframe computer of NAND Flash makers are investing billions on a wing and a prayer, and so far, they have done OK. Losses, where they have occurred, are a pittance compared to those of DRAM makers. Once free-falling in price, the NAND market has usually recovered quickly (and periodically, so it has not been down-down-down)....as anything growing that fast will. Wait one quarter and the demand will automatically absorb 28% more output, or liquidate an apparent supply excess of the same magnitude. It takes minutes to drain the swamp when the current is so swift.

So, not infrequently, NAND makers swallow hard, check their cash flow, assess potential for their own cost reduction, say a prayer to the Gods of NAND Flash demand and put the shovel in the ground. They take on faith and some not inconsiderable hope, that NAND demand materializes as fast as supply does. So far, the NAND demand is pretty much OK, but there is always the potential for a major overshoot, for which demand (incremental or new demand) cannot materialize rapidly enough, and an overhang persists, driving prices into the pain zone. Capacity is growing so fast that market equilibrium and price stability may be way behind you before you realize that there are not enough applications (demand) to take away all the output.

Sources of GB production growth for 2008: For 2008, three-bits per cell will make only a small incremental contribution to bit growth; most will come from more wafers (square inches of silicon)...accounting for more than 60% of the GB growth, and from litho shrinks ...for the remaining 30-35% of GB growth. Cleverness of multi-bit cells, and improved lithography have their own cost, but it's the 'more wafers' that drive the NAND investment budget, making NAND CapEx investment in 2008 close to where DRAMs are, at more than $13B, though the DRAM market in larger in revenue terms by 50%. In the crazy semiconductor economics of 'building for the future', NAND makers' CapEx for 2008 far exceeds their NAND profits for this year, and rivals their expected total NAND revenues. For their sake, there better be large markets out there to absorb their planned boost of 150%+ in GB production. Compared to DRAMs in 2008, NAND investment has been largely unaffected by tough pricing and the threat of a supply overshoot. DRAM makers, on the other hand, have cut back significantly to try to restore market balance, and profitability.

Although mainstream PC makers have yet to embrace DDR3 DRAMs, and DRAM makers all have rather broad initial DDR3 DRAM and DIMM portfolios, there is still a lot of smaller volume interest from users who find both unparalleled performance and lower power than they can get from DDR2s. The fact that DDR3 is more costly than DDR2 DRAMs, usually by 2-3x, is lost in the system BOM wash, as fewer DRAMs are being used in these early adopters' products as they launch their systems to market, but prices are expected to drop to parity or lower than DDR2 once volume builds. In addition, DDR2 DRAMs are also relatively power-, performance-, and feature-constrained compared to DDR3.

A quick look across leading PC, server, and workstation makers in mid-May found NO advertised systems using DDR3 DRAMs, though there were some which advertised DDR2-800 and a few with overclocked DDR2-1066s from Corsair as 'standard' options. While HP-Compaq, Lenovo, Dell, and Acer may be too conservative to jump into DDR3 prematurely, there ARE PCs available from 2nd and 3rd tier PC suppliers which are using DDR3 DRAMs, mostly "White Box" makers.

The ranks of DDR3 DRAMs and DDR3 DRAM DIMMs which have been validated by Intel are also large, as is the existing portfolio of DDR3 or DDR2/DDR3chipsets, motherboard support for DDR3, and the other accoutrements which give life and benefit to PCs with DDR3. Most DDR3 available today is DDR3-1066 and 1Gb density or higher; DDR3-800 and 512M DDR3s are probably already consigned to the dustbin of history. Like DDR1 and DDR2 before them, the earliest versions, the 'proof of design and bragging rights', were null and void as production vehicles almost from the start.

Today's DDR3 market conclusions:

1. There is NO DDR3 in significant quantities in PCs , servers or workstations yet, and none at all in the PC Majors' products...Dell, HP/Compaq, Lenovo, Acer.
2. DDR2-667 constitutes the mainstream DRAM in use, but DDR2-800 is present in large volumes. DDR2-1066, despite achieving the extraordinary feat of being a late-add to the JEDEC DDR2 specification, and being supported by chipset makers and some MPU suppliers, is still confined to the 'overclocker/enthusiast' niche, with high price premiums and low volumes.
3. According to DRAM Exchange, DDR2-667 and DDR2-800 are priced about the same, showing, as we saw with DDR1, that the manufacturer's yields a faster than the demand coming from the market: HS parts are not scarce, at least up to and including -800.

Short observations on DDR2 DRAMs in PCs: The first DDR2's took over from DDR in PC systems offered by Dell in summer of 2004, and were DDR2-533; the only sustained use of the slowest speed bun for DDR2, DDR2-400, was in servers, which rely on mostly custom chipsets and decidedly non-commodity and non-PC system architectures to get bandwidth out of their DRAMs. Dell has been Intel's early market lead-in for various products, and it was felt that this move by Dell, though the system performance benefits were arguably non-existent, would get the DDR2 DRAM market kick-started.

History showed, however, that this move only created a substantial confusion as to where the market was headed, and many, if not all DRAM makers, sloshed their wafer start mix back and forth between 'incoming DDR2, the DRAM of tomorrow' , and 'yesterday's DDR', creating confusion for DRAM makers, in relative DRAM pricing and supply-demand balancing. 'Crossover' in pricing between DDR1 and DDR2 took place several times, going both ways, as the market searched to equilibrium and direction.

All this happened until everyone came back to work after the Christmas holidays in December 2005. Early 1Q06 found DDR2-667, with a measurable performance benefit in wide and widening use in PCs. In fact, this probably marks the start of the true DDR2 DRAM era, not 3Q04.

On this point, AMD, which added the DRAM controller onto the MPU for this transition, strategized correctly and continued to ship competitively performing Athlons and Opterons into systems that still used DDR1 as their DRAM memory, and to gain MPU market share at the expense of Intel.

Today, as noted above, the PC world is still largely DDR2-667...some of which are truly DDR2-800 downbins. Today, in mid-2008, 30 months after DDR2-667 rose to the top of the DRAMs-into-PCs heap, makes one wonder about the benefits of even having DDR2-400, 533, (667), (800), 1066 and 1066+ superbins. For sure the major DRAM-using segment ignored all but DDR2-667. By most measures, no benefit of DDR2 over DDR1 in PCs was evident until DDR2-667... enabled by all the associated chipsets, HS bus and other system changes that had to, or did, change at about the same time.

There may be an important lesson here for DDR3, which by most prognostications (for the PC space at least), is way behind in market penetration, in achieving price parity with DDR2 (why shoot yourself in the foot?) and presenting an indisputable value proposition to PC makers and their customers. Early 2008 DDR3 optimists were looking for 30% DDR3 penetration and DDR3 prices to be within 10% of DDR2 by year-end 2008, which, at this point in mid-2008 would be considered (a) impossible and (b) foolish, respectively.

Denali's view of DDR3 in PCs: So, let's say DDR3 will be between 5-8% of DRAM production as we leave 2008, and prices MAY be only 1½ to 2x those of DDR2. Let's further submit that DDR3-800 and 1066 are now almost surely dead letters, 512M is already history (and not just for DDR3), 1Gb DDR3 will probably be a minor play, and that the PC DDR3 DRAM market will first gain traction in a quantum leap to DDR3-1333 and 2Gb devices some time in 2H 2009. It is hard to see it coming together much faster than that, and much of the early DDR3 work on chipsets, mother boards, enablement and validation, as well as Gen I and Gen II DDR3 DRAM designs, will have been (almost) for naught. DDR3 may see its first truly production part in the sub-60nm or '53nm' node, where it delivers a demonstrable performance advantage to a PC world whose attention has shifted to more to low cost, low power, low 'birthweight' .... and continues to support windows XP.

Next week's DMR: DDR3 in embedded systems is completely different, quicker ramp, improved value proposition, clear product benefits. For example, Denali's Databahn controller for DDR3 DRAMs has dozens of design wins already, across most market segments. We'll tell you what we're seeing in the next DMR.

"NOR" Flash for Server Memory, not DRAMs?: Spansion’s recent announcement, with Virident (a local SilVal start-up), of a server NOR-based MirrorBit flash memory as a low power alternative to DRAM memory in data servers, was a many-faceted launch of a new direction for flash and a clear response to the emerging concerns that server farms are quick becoming power-out-of-control. The formal presentation, which can be viewed (approx 1:15 hrs) at the Spansion website, marks a new direction for servers, for flash in server memories, for NROM/MirrorBit technology, and provides many datapoints about the extent of the Data Center memory power problem and economics which EcoRAM is designed to address.

Though almost all LP DRAMs go into cell phones and PDAs today, servers and data centers, where costs and power are more visible and equally as critical, are driving a large interest, too. Several presentations at Denali MemCon in the past few years have focused on the Data Center Power Problem.

But it is not ready quite yet.

Those of you who have watched Spansion develop this NROM/MirrorBit technology and bring it to market in the majority of their NOR products (and some custom extensions of pure NOR, such as ORNAND and MirrorBit Quad Eclipse), to become the market leader in the cell phone NVM space…but have simultaneously been concerned about “where they go from here”, will probably not rest much easier with this new ‘technology announcement’. Spansion’s shares are not down 80% in the past 12 months for nothing, though profits (losses) are running about the same over that period.

It seems, no one really knows what happens next at Spansion, though they continue to be one of the largest NVM suppliers to the phone business, even with the entry of Numonyx earlier this year.

It will take another year or so to separate the wheat from the chaff insofar as how much innovation, market acceptance, potential for market dominance, and dare we ask, profits, Spansion can bring with this unique technology co-developed with Saifun, which they bought in its entirety more than a year ago.

EcoRAM is a custom flash memory design, built on Spansion’s 65nm-to-be-45nm process, which is essentially a NOR flash, but with the design customized so its operation insofar as writes and reads, makes it look like a DRAM in systems, only denser by 2x, far lower power (1/4 per MB), and equal or ahead in process ground rules compared to DRAM. There is no public data sheet for EcoRAM, and product is not available to customers, though enough have been built to achieve ‘proof of concept’ in a true-life server application, which was demonstrated during the presentation.

EcoRAM’s endurance is 10,000 cycles, but with proper software (Virident), bad blocks and bits can be foreseen and guarded against ahead of failures. Like DRAM and NOR, but unlike NAND flash, EcoRAM has XIP, bit-read and write access, and truly random access capability. No refresh current (power) and non-volatility are two important distinguishing flash features, compared to DRAMs used in server applications.

Background on Server Issues and Trends: As backgrounder for this announce, Spansion and its partners provided many dimensions about server farm power consumption which are useful.

Google has about 1M servers in operation today and are adding 300-400K/year; Microsoft has 400K and is doubling every year.

One watt of server operating power takes about another watt of air conditioning power to get rid of the waste heat; so, reducing server power utilization saves two watts of power for the enterprise owner. The clear message in the slide above, which lays IT DRAM power consumption (demand) against the installed base of US Solar Power's supply shows the stakes, and potential gain, from shifting from DRAM to EcoRAM in the serever universe. EcoRAM, if applied universally to all Internet Servers in the US, would reduce power demand more than the power contribution of the existing installed base of solar energy today.

Today in servers, MPUs use 25-50% of the total operating power, but the recent moves to dual- and quad-core MPUs, 64-bit architectures, integration of the memory controller onto the MPU, virtualization and dynamic clocking, have shifted a larger fraction of the server power to the memory, which ratio today is about 2GB/MPU core. Since servers have huge memory configurations to support so many cores, memory power has gone up in proportion and in absolute terms…total memory power consumption went up while MPU power consumption, despite far more processing performance, has remained close to constant.

The mad rush to redefine MPU Performance (= goodness, = high price, = value) from “GHz” to ‘instructions/watt’…almost in an instant… has had no such similar effect in memories, though the Spansion EcoRAM comes close to setting the bar at “Data transfers/watt”, or “GB/watt”. Clearly, the MPU trends of the past five years have put added pressure on memories to avoid being the ‘server power bad guys’, and so far, they have not responded. EcoRAM is one solution; perhaps LP DDR2 DRAMs, which should be in high volume in 2009, are another. LP DDR3 DRAMs, still many years away but whose definition is being discussed today, will certainly pay major attention to the power needs of the server space, where the costs are clearly evident, and significant.

Unfortunately, the technology outlook for the NROM MirrorBit, in terms of its true cost of production, scalability, read and write speeds and endurance…and long-term market acceptance… are all uncertain at this point. No one knows if some other memory technology or memory system approach is percolating in the background which is better and will come to market before EcoRAM gains traction. No one seems to have mastered the MirrorBit technology except Spansion…all its technology licensees have truly failed to bring the product and technology into stable, high-yielding mass production.

There are strong, critical voices of Spansion’s technology roadmap, among their competition; SanDisk and Intel suggest that the basic technology is doomed to be self-limiting or run into insurmountable technical roadblocks. Spansion has provided little public information to assuage its critics, though their strong and continuous presence in the phone NVM business is an important voice in their favor…someone keeps coming back for more!

Further, MirrorBit, for all its laudable attributes, has failed to be Spansion’s corporate salvation, as they are oozing red ink every quarter in an admittedly-tough NOR flash business environment. The advertised 40% fewer critical manufacturing steps when compared to floating gate NOR approaches has to help…but now that Intel and ST have become hidden financials as ‘Numonyx’, accurate cost comparisons have become more difficult.

On the other hand, Spansion was successful in bringing up SP1, its 2000 ws/week 300mm line in Japan, to 65nm over the past nine months, and will have 45nm running by year-end 2008. They have 32nm MirrorBit NOR pilot product running in the labs. They have made business adjustments of ‘make or buy’ to better focus their capital and internal development effort. They have internalized some NOR production and outsourced some non-critical and legacy parts to qualified third parties. And not a peep has been heard from Saifun since their acquisition by Spansion more than a year ago…no new technology licensees, no new income stream, no technology breakthroughs. With a full plate, a tough competitor and tough market, and limited cash, they are stressed to the max, or close.

But, with this announce, there is now more upside potential for Spansion, but timing being what it is, we will wait some more until some of these bold technology initiatives bear some real financial fruit.

Despite a weak start and fuzzy LP DRAM Roadmap Edges, LP DDR2 promises to be a blockbuster product, correcting many deficiencies of LP DDR1 DRAMs.

Setting aside all of the shortcomings and missteps taken by the industry in its march along the LP DRAM roadmap (See DMR), the upcoming LP DDR2 DRAM products promise to be blockbuster designs which will almost certainly service a large fraction of the power-conscious DRAM-using applications base. Many of the deficiencies of the LP DDR1 and first generation LP DDR2 DRAMs have been overcome, theoretically now, but with high expectations that the ‘fixes’ are real and technically feasible; LP DDR2 was originally conceived to be more performance and less power than its LP DDR1 predecessor, but changes since the provisional design concept of what it would entail, have made it even more so.

This also bodes well for the emergent “Performance Mobile” segment, which has grown along in lockstep fashion with the sales of high-end phones with both camera and internet access functionality, as well as products containing GPS. It is no longer a choice between high-performance and low-power; an increasingly large fraction of applications need both.

Changes and remedies: LP DDR2 DRAM voltages have been dropped not just from 1.8V to 1.5V, but all the way to 1.2V, taking a double-down step, compared to DDR2 PC DRAMs, which use 1.8V. This automatically brings the power down by more than half. Datarates, compared to LP DDR1, will be more than doubled through use of improved IOs, and moving to a four-bit prefetch.

Though the early offerings for LP DDR2 DRAMs were weak, they are being replaced later this year with improved products from all DRAM majors, with datarates up to -800Mtr/sec, and maybe higher (Hynix’ LP DDR2 DRAM announcement (see Hynix) clocks out at -800, and is targeting year-end availability. Others feel confident in reaching the -1066 speeds, once the product starts rolling out.).

Both of these features were adopted in response to market requirements, and were based on the experience in the prior several years.

Broader range of densities available: What’s more, the LP DDR2 DRAM roadmap itself addreesses another of the problem areas faced by the LP application set over the past several years…lack of lower density products. LP DDR2 DRAM specs are expected to run to as low as 64M, a low density available only with SDR LP DRAMs, and the thinnest support at DDR1, with nothing at all for PC DRAMs.

Will “ALL” DRAMs be LP DRAMs in 2012? So fast is the whole “LP Space Concept” changing, as well, in is more universal embodiments, LP DRAMs are now being viewed in some quarters as replacement for large portions of the PC DRAM marketplaces…only desktop are safe from encroachment, as servers and laptops have significant power concerns that can be addresses by LP DRAMs…at the right price. In another wave of the market, something of yet another resetting of the ‘Personal Computer’ taxonomy is underway, with the advent of Ultra-Low Cost PCs (ULCPC) and UltraMobile PCs (UMPCs), as well. This year or next, laptops will constitute more than 50% of PCs sold, many of which compete right on the desktop with larger systems, but with mobility, batteries, slightly smaller screen sizes, and little loss of functionality compared with their larger brethren.

So, LP DRAMs may become not only the lowest power DRAM, but the volume seller, and, consequently, the cheapest, as well. For technical reasons and a highly-fragmented marketplace, subflavors of LP DRAMs will continue to exist, limiting the market’s ‘commodity nature’, for sure…But instead of LP DRAM remaining confined to cell phones and PDAs, as LP SDR and LP DDR1 DRAMs pretty much have been until today, by 2012, variations of LP DRAMs could be half the DRAM market.

Fuzzies remain, nonetheless: All that being said, however, uncertainties and ‘instabilities’ remain in the Low Power roadmap. (1) The concurrent establishment of the LV roadmap (see LV DRAM Chart), to capture, belatedly, the appearance of reduced-voltage DRAMs (like those from Qimonda and Micron), which stepped down operating voltage faster than the PC DRAMs, but are still able to hit the market requirement for product speed, is one direction that developments may take. (2) Wider tolerances from the spec can enable ‘spec’ LP DDR2 DRAMs which are capable of full-LP DRAM-spec performance down to 1.05V or 1.0 V, ergo, lower power, for free. (3) And nothing is to prohibit an ‘off spec’ LP DRAM with operating voltages UNDER 1.0V; when SRAMs were the “LP King” in wide use in the 1980s, no true standards existed and vendors competed with a variety of reduced-operating voltage parts, down to 0.8V, plus a lot of special processing to minimize power.

For sure, even today, the design choices of LP DRAMs are moving in many directions, concurrently, and it does not appear to be likely to settle out any time soon, as LP features are showing up in PC DRAMs (like TCSR and PASR in DDR3, as an option), multiple voltage domains across the chip, innovative circuit designs, and a general effort to be “Best among Equals” by vendors, to avoid the worst commodity nature of PC DRAMs, to evolve a product line suitable a for a wide variety of applications, and to not have Powerchip come in 3 cents lower on price and knock out your hard-earned design win.

LP DRAM Market Status & Market Drivers to Date: The basic concepts and feature set for the Low Power DRAM roadmap were set down nearly ten years ago, and had the following basic requirements: (1) The LP DRAM roadmap would lag the ‘PC DRAM’ (mainstream DRAM) roadmap by about one architecture (i.e. three years), and LP DRAMs would have several required features: (a) Temperature Compensated Self-Refresh (TCSR); (b) Partial Array Self Refresh (PASR), (c) advance the voltage reduction one level past the PC DRAMs, e.g. when PC DRAM went to 2.5V with DDR1, LP DDR DRAMs would go down to 1.8V; when DDR2 went to 1.8V, LP DDR2 DRAMs would be 1.5V; etc., and (d) LP DRAMs would have a well defined Deep Power Down Mode...turning off power altogether.

In an industry known for not being able to see more than a month in advance in terms of market trends, twists and turns, much less forecasting the technical tools to implement any plan, this was a bold, and for the most part, successful bit of insight and challenge. In that era, cell phones were a nascent 160MU/year market, and have now been running at more than a 1.0B to 1.2B units/year clip for 3-4 years.

Mobility, and its attendant demand for long battery life, undiminished performance and features, has been THE MegaTrend in chips for the past decade or more, taking over from the 1980’s-led PC era of WinTel, which, though PCs are still the largest revenue market for chips, has been reduced to ‘normal market evolution’ today. Everyone got their PC years ago, and though almost everyone also has a cell phone today. But phones are evolving more rapidly than PCs, adding features, and driving technologies. So drawing a line in the sand, and staking out a technology direction for Low Power DRAMs, so long ago, was timely, much needed, and beneficial, and has served its purposes remarkably well.
This roadmap served the industry well through Low power SDR DRAMs (running concurrently with the use of DDR1 in the mainstream PC space), and Low power DDR1s when the PC space was using DDR2, etc. But for a long time Low power DDR1s had a hard time hitting the fastest speed bin…LP DDR1-400, and a half step, to -366, was proposed, accepted and became a standard for a time. Even today, the LP DDR1-400 spec is not well supported, even as Low power DDR2s emerge. The prospective “three year” time lag behind the PC DRAMs, has also started to look a little ragged in terms of product availability and take-up in the market, as well as (increasingly and emphatically), hitting required performance levels.

Below we have ‘borrowed’ and adapted a chart presented by Elpida at Denali MemCon Japan late last year, showing the estimated market mix of LP DRAMs by various competing architectures In a nutshell, LP DDR1 is in the process of replacing LP SDR DRAMs, and LP DDR2 is “not here yet.”, but is expected to gain traction within two years. Other presenters suggested that nearly ALL LP DRAMs today were used in cell phones and PDAs, though in phones, they share RAM honors with SRAMs and PSRAMs, but of which are in steady decline today as LP DDR1 DRAMs ramp forward.

Source: Elpida at MemCon Japan, 2007; Denali

LP DRAM New Challenges, New Markets, New Tools: But life does not stand still, technology does not always give way as we foresaw years earlier. Once the industry engaged in the task of driving down power in DRAMs, it saw many alternative paths to take… as well to respond to a diversity of applications requirements and device LP enablement methods. And staying on the original roadmap, which necessarily had many “TBDs” on it in terms of “how we expect to achieve this and that”, has not always been as easy or as possible as anticipated.

Today, lower power solutions are being sought in new circuit designs, improved process flows and chip designs, in simple changes in layout (as from x32 to x64 designs), and in borrowing the lessons of other ‘roadmaps’ and products. Unexpected problems are being encountered (the difficulty in reaching high data rates), and the shifting sands and demands of new markets are making it harder for ‘one-size-fits-all’ solutions. LP DRAMs, to date largely confined to cell phones and PDAs, are chomping at the bit to get designed into mobile computers of various sizes.

Today, there are NO Low Power DRAMs at all in the formal laptop segment, which market constitutes the largest GB/year market for ‘mobility memory’: 125M Units x 1.7GB/system easily trumps 1.2M phones with 32-64MB/system, as even flash is making a serious run for the LP memory role in phones daily.

In short, the Low Power DRAM roadmap is running into problems, even as attractive LP features are being picked up in more traditional DRAM products. Also, the hard lines separating one class of products, and differentiating them from one another, are blurring. In fact, I believe that not only will the Low Power DDR2 DRAM of 2012 will look far different from what we see launched today, but there will be a variety of prospective LP solutions for the similarly bewildering array of power requirements of the industry. “Power reduction” interest is pervasive throughout the industry today, and though the LP DRAM roadmap can serve many or most of those interests, many applications are likewise finding their own ways to keep power down, inside or outside the confines of the LP DRAM roadmap.

“DRAMs” or “Memory” is only a part of the system power problem, and only a part of the solution which system architects face today. To see this, look no further than Intel, which has launched in the past 3-4 years, major ‘back to the bare metal’ redesign initiatives aimed at power reduction in their MPUs, with some major business successes resulting (forty years on, I never cease to be amazed at Intel’s successful technology initiatives): Banais led to their Centrino product line, and their most recent initiative led to their Atom processor for the Ultra Mobility Sector…already sold out, over-subscribed, over-designed-in and a certain money-maker and market success for Intel.

LP DDR2 DRAMs offer a solution: Despite the shortcoming-to-date of the most recent LP DRAM product initiatives, there is a strong motivation and interest in getting the LP DRAM back on track. A task force within JEDEC is in the final stages of creating a spec and many vendors will have LP DDR2 DRAMs, up to -800 versions, by the end of 2008..much higher performance and much lower power than even the best of the LP DDR1 DRAMs now avialable…twice as good on both counts is a reasonable expectation: namely, twice the datarate at half the power. This work is being driven largely by phone makers and, of course, supported by the technology roadmaps of LP DRAM vendors. There is also associated work to support server DRAMs with lower power versions (formalizing the steps, and voltage step-down steps, already taken by Qimonda and Micron)

Can LP DDR2 DRAMs give the industry what it needs for next-generation, high-performance low power systems? Can it regain the momentum the LP DRAM roadmap needs, to satisfy a large fraction of the industry’s low-power memory needs? Or are the needs too diverse and the timetable too uncertain, that users will not be able to wait for Golden LP DRAMs to appear at reasonable prices?

Examples of what activity is going on in this area today include:

Server DRAMs: Qimonda and Micron’s 1.5V DDR2, taking the generation-to-generation voltage step-down one step further (or viewed another way, applying the LP DRAM voltage spec to what is otherwise a PC DRAM.) Since some DRAM applications do not need the speeds available in traditional (Standard) DRAMs, vendors find that they can get enough speed and lower power just by dropping the voltage; As it has been the case for some time, the speed distribution of DRAMs manufactured is much faster than what the market needs; there is no price premium for DDR2-800 over DDR2-667, just as DDR1-400 cost about the same as DDR1-333. Vendor cost reduce to improve their finances, the speed comes about for free. So why not take a different tack, and make a lower-voltage, lower-power, sufficient-performance DRAM family?

Start-ups aiming at LP RAM technologies and markets: NanoAmp (now a part of AMI) and ZMOS ‘back to first principles’ RAM roadmaps (recall that SRAMs were the SOLE RAM for all the watch and calculators in the 1970s and 1980s, and were used in early generations of PDAs even in the late 1990s.) These two companies were launched and built on the emerging need to take an original look at the needs of the LP market and not be constrained by ‘what other people, or the industry groups, were doing.” NanoAmp is SRAM focused; ZMOS uses advanced circuitry they developed to drive power down in DRAMs.

Back to “Cleverness”: All LP DRAM makers are very clever in the ways in which they can drive a few microamps of power out of their DRAM and SRAM designs. From what’ been seen so far, Elpida is one of the best, and is seen as a major LP RAM innovator. They launched an “ECC-enabled” Low power DDR1, which reduced refresh rates and, therefore, refresh currents, and then corrected out bits which were dropped. Hynix has followed with a similar solution.

Elpida also announced a x64 LP DRAM, which give the user the bandwidth without have to move to higher frequency, which seems to be the cause of most LP DRAM performance limitations today. Achiecing high bandwidth with wide buses, not fast clocks is an important LP memory and system design tool.

Jumping the tracks: LP features jumping out of the LP Channel into the mainstream: The industry standard DDR3 DRAMs have adopted, as an option, the PASR and TCSR features which were mainstays of the original LP DRAM roadmap. LP becomes mainstream and not nichy…but not for everyone, either.

Qimonda, in its new and agressive DRAM roadmap, extols the LP virtues of its Buried Word Line architecture (not to mention its small DRAM cell size.)

Source: Qimonda

Dense SRAMs are also resurgent in taking on the LP RAM marketplace, esp. for lower densities which may not be well served, if at all, by LP DRAMs…64M and even 128M, with higher datarates than SDR DRAMs are capable of. Renesas now offers 64Mb SRAM with 55ns access times and low power; lithography already successfully employed in DRAMs would suggest that higher densities of LP SRAM are achievable in the near future, curing some deficiencies in the industry’s low density “DRAM” support.

Embedded DRAM Potential for Super LP Systems: Another possibility that is coming into focus for some applications is that old whipping boy of memories that refuses to go away. It is the embedded DRAM, or eDRAM, which is said to be present in more than half of ASIC designs in 65nm and finer design rules. At 65nm, which is available from most ASIC vendors with eDRAM (IBM, NEC, Toshiba, Samsung, TSMC), the user can embed 250-300Mb of DRAM…which is in a part of the LP market space which is ill-served by existing standalone DRAMs, either SDR, DDR1 or DDR2…the lower densities needed only for applications that require an LP RAM as something of a ‘system cache’, and not as a ‘mainstore’ of significant size. Once 45nm is up and running...and it is ramping today…the available eDRAM densities will be greater still. Certainly, 64MB of eDRAM is within reach.

Embedding the DRAM into the ASIC/SoC, increases user options and gets around some of the performance limitations of standalone memories: One can design in a 256-, 512-, or 1024-bit bus and turn the clock down low, reducing overall system current. The high currents required to move data off the chip to the MPU-host is also reduced significantly. Since it is system power that is usually the issue, and the memory is toggled into its LP mode by external commands, this places the (e)DRAM right inside the ASIC, which can improve memory power management by the host, and perhaps make possible more “LP Modes” and “LP Methods”.

As most eDRAMs were originally optimized to replace very fast SRAMs in on-chip caches, rather than low power, this constitutes a new (or resurgent) direction for eDRAMs, which is totally in line with what most foundries now have in the process flow: a high-performance process flow and a Low power process flow.

The vast majority of cell phones today moving towards using LP DRAMs of 256Mb density, so eDRAM should be an option, based on that fact alone.

Double Down Voltage options: Some vendors are looking at a double reduction in voltage…using 1.2V for LP DDR2 instead of 1.5V, finding that they either can hit the speed with lower voltage, or that lower power is more important in their applications than the higher speeds. (This is another issue…the relative importance in applications of performance v. power…some need one more than the other, which is not to say, there is an emerging class of applications which need lots of both.

This Low-Voltage with LP Features trend is both new and sometimes confusing to users. For reference, here are the I/O Volatage standrads for the several DRAM roadmaps in place today.

a: Low power DRAMs (LP DRAMs) all have (1) TCSR, (2) PASR, (3) advance voltage
reduction one more step compared to PC DRAMs, (4) Deep power down mode

b: Low Voltage DRAMs have voltage stepped down one increment from PC DRAMs,
but are otherwise functionally the same

*: This recent standards decision to double down the LP DDR2 voltage, to 1.2V
instead of 1.5V, was a departure from the earlier LP DRAM roadmap, in order
to get further power savings, without compromising performance for most applications

For most voltage standards, datasheet tolerances are "+/- 10%"

Many or most products also use several voltage domains on their chips

We do not have a lot of high expectations that this chart will remain stable for too long, or will encompass the totality of Low power DRAM offerings; once 1/2V is mastered, why not offer a 1.0V or 0.9V specialty part (or one that has a user-selectable 1.0V 'option')? Do the benefits in 'LP' or 'performance' of using a x64 chip justify its off-roadmap character? Which applications cannot get enough LP from a 512M, x32 LP DDR2, or not enough performance, that they need to (and can cost-justify) a specialty LP DRAM? In some ways, this question looks much like that faced every few years with the graphics markets.

Summary and “Market Direction”: We have little doubt, today, that LP DDR2 DRAMs will make a very strong appearance by the end of 2008; there is too much inertia, interest, and the stakes are too high for it not to happen. But it will be difficult to get fully-compatible multi-sourcing among vendors, and exact-spec commonality. The nature of the market demands and succeed on competition in secondary parameters, and metrics. So, despite "JEDEC" LP DDR2 DRAMs being THE high volume roller for servicing the LP DRAM market in 2010, diverse applications and requirements will combine with diverse LP chip design methodologies to make a fragmented “LP DRAM” market that will defy efforts to keep within the channels of some finite set of features, standards and conventions.

Somewhere along the line, the small and maximum-portable end of the PC segment needs to get an LP DRAM roadmap of its own, optimizing its performance and power requirements, even as it has avoided the traditional LP DRAM roadmap so far.

IMFT to 34nm NAND production: Micron and Intel, two partners in NAND Flash Manufacturing IMFT JV, announced an industry-leading 34nm NAND flash product launch yesterday, in a 172 sq mm 32Gb MLC NAND flash die, that catapults them into the process geometry lead among NAND makers, and thus completes the IMFT Business Launch phase, which began 11/05 with the announcement of their IMFT Joint Manufacturing venture.

They have working 34nm silicon in the hands of key customers and flash controller makers, and will ramp the process and product, using essentially the same 50nm tooling, beginning immediately.

In the meantime, they have marshaled the considerable resources of both players, usefully absorbed idle capacity at Micron’s Manassas, Boise and Lehi fabs, and built out Manassas and Lehi with state-of-the art 300mm/50nm process tools. They also have brought a greenfield fab shell to “equipment readiness” in Singapore, established a NAND market presence for both parties, incl. flushing out former NAND suppliers from Micron’s down-channel retail “Lexar” brand flash chips. Both companies’ sights are set clearly on the nascent SSD marketplace. Intel’s very deep IP portfolio and experience in EPROM/Flash multilevel cells is now combined with Micron’s penchant for low cost manufacturing, to make a formidable competitor in the NAND Flash marketplace. In the present quarter, 2Q08, IMFT’s partners, Intel and Micron, are expected to sell more than $500M in NAND flash, taken to market ~50-50 by Intel and Micron. This is still way behind Samsung, Toshiba/SanDisk and Hynix in volumes, but safely in fifth place, with arguable advantages in process ground rules and technical know-how, plus product quality and QOS for the demands of the SSD marketplace.

They have come a long way in a short time, but, as if oft said, “The past is merely prologue” for what lies ahead. For chips, and especially memories, “What will you do for me tomorrow?” always combines with “past performance is no guarantees of future returns.”…so what they have is now an even start.

IMFT is now in the running in the NAND Flash market in a big way, if not in total volume and market standing, then certainly in terms of demonstrated technology. They have come a long way from a dead start and empty fab shells only a little more than 24 months ago.

Fabs and capacity: Micron has a higher percentage of their NAND flash capacity running on 300mm wafers than any other NAND maker, having upgraded their existing 200mm capacity, exc. Boise, which remains 200mm. Increasingly, the superior production of 300mm wafers is seen as a sine qua non of memory manufacturing, and more for NAND than DRAMs, which continue to have legacy and differentiated products that can be made cost-competitively on back generation tools and processes.

Today, Micron has about 100K/mo. wafer starts (300mm =), in its Lehi, Boise and Manassas fabs. With Singapore, which is now slated to start ramping by mid-2009, they will be adding 60K/month more when fully ramped in mid-2010.

Production volume: With most of their output today being built with 50nm processes (the remaining 15% is 72nm), IMFT appears to have about 13-15% share of GB shipments and a similar fraction of NAND revenues. Their GB fraction is somewhat depressed by their late entry into MLC NAND flash, based on their share of wafer starts, but this will be worked through in coming months, and subject to their customers’ requirements for either MLC or SLC. One of Intel’s and Micron’s strategic target markets is SSDs, which themselves are caught somewhere between needing SLC and satisfied with MLC, provided performance and endurance issues are suitably hidden behind controller and error-management software in the controller.

Downstream channels: SanDisk claims the high ground here, with the only silicon-maker recognizable name to the general public besides “Intel”. But Lexar, which became a part of IMFT at its conception, is a substantial player on the retail shelves of Best Buy and Circuit City, and Crucial (Micron’s internet downstream DRAM DIMM provider) both give IMFT/Micron direct lines into the retail channel. This can give them more assured homes for their product output, end-market pricing flexibility, the ability to manage their inventories with price adjustments at the retail channel. This is NOT seen as a way to ‘cut out the middleman’s profits’, as some claim, since Micron IS the middleman and the middleman always has to get paid, whoever it is. It is much more a “product flow control issue”…

Process and technology; controller technology, MLC: The initial pooling of interests between Intel and Micron when IMFT was launched had both parties putting in some funding, Intel putting in its NVM IP, Micron transferring NAND designs to Intel (some kind of contribution-balancing and financial shenanigan for patent protection and ‘contribution balancing’), and Micron transferring ownership of a nearly-unused Lehi fab (built in 1995, and moth-balled 1/1/96), the vacant half of their Manassas Fab (bought from Toshiba in 2002 to make DRAMs and never fully built-out), as well as an offer of their original Boise, Idaho fab to make NAND on 200mm wafers. They steadily brought their technical horsepower to market, one stage at a time, moving from 72nm process (well behind the market) to 50nm about 18 months ago (arguably leading edge) to their 34nm process announced 5/29. They delayed the ramp of MLC NAND until early this year, though the basic technologies were understood well before that, so as not to confuse the technical challenges they faced at any given time.

Both parties have flash controller capabilities and Micron has been shipping Managed NAND since the beginning of the IMFT Venture. They will sell raw NAND wafers, die and packaged NAND modules, plus NAND assemblages with controllers, depending on the customer and application. They also have a stable of third party NAND flash controller makers with whom they work. The sense within the industry is that controller makers MUST have access to the NAND silicon to make important design decisions such as use of ECC and wear-leveling strategies.

All in all, this has been a remarkable feat for IMFT, investing into a market of plummeting flash prices, bringing up and stabilizing all the various technical processes, and getting into competition even with a years-late start, against some of the most agressive technical horsepower in the industry today.

Now the real action starts.

Hopefully, this is the bottom of the market, but only time will tell

Memory producers had predictably bad 1Q08 financial results, with DRAM prices low and lower and NAND prices dropping 30-50% from 4Q07 to 1Q08, depending on who is doing the talking. All in all, revenues for memory makers tracked in our worksheet dropped 13% from 4Q07 and profits (or losses, as the case may be) continued their slide, and exceeded about $4B. A few smaller companies and those outside DRAMs managed to keep their heads above water. Sales and profits are shown in Table 1 below (all values are millions of dollars):

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