| Key Features |
- NEW! Full support of PCI Express version 1.1 and Gen II (revision 0.7), including
- Speed Negotiation to support 5.0 Gbps data rates
- Link retrain to wider link width
- Inferred electrical
- Access Control Service (ACS)
- Function Level Reset (FLR)
- PIPE Gen2
- Full timing, bus functional modeling of PCI
Express Specification
- Multiple testbench and language interface
-Verilog, VHDL, C/C++, System C, e, OpenVera
- Monitors for interoperability testing
- Controllable rule checks matching PCI SIG*
Compliance Checklist
- All PCIe layers supported
- All PCIe device types supported
- PCIe power management supported
- Direct access to configuration registers
- Detailed coverage of functional layers, including
clock recovery
- Supports all revisions of specification
- Industry's most comprehensive compliance suite
- User-customizable packet generation
- Pre-defined traffic libraries
- Powerful error injection capability
- Cumulative functional coverage reports
- Easy design and verification integration
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| Fabric Topography of the PCIe Model |
PureSpec for PCIe models all PCIe devices in the topology, including the root complex, switch, endpoint and PCIe to PCI bridge. A generic device conforming to the specification can also be emulated. Composite configurations by port, function or virtual channel are also supported. A library of common PCIe device configurations are available online from Denali.
| Protocol Layer |
Model Highlights |
| Transaction Layer |
Completely models protocol, plus manages transaction requests and completions. Checks for all the packet rules. Supports message requests as well as multi-functions. |
| Link Layer |
Completely models protocol, + manages data integrity (CRC), supports flow control initialization. |
| Physical Layer |
Completely models protocol, plus supports power-on-state machines and training sequence, and clock recovery. 8b/10b encoding and data scrambling are modeled. |
| Configuration Registers |
Maintains configuration info in a separate memory space. Supports register queries and updates through a testbench interface. |
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| Data Generation and Compliance Suite |
PureSpec for PCIe provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to PCIe specifications. The highly integrated nature of PureSpec for PCIe's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT.
PureSuite, a companion product, is a complete test suite covering all PCIe compliance checklist items. With thousands of configurable, directed tests, it is capable of exercising your design from both the PCIe interface and the design's application interface. Coupled with PureSpec for PCIe™'s assertions coverage capability, PureSuite helps to measure the compliance and interoperability of your design.
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| About PureSpec |
Denali's unmatched EDA modeling and verification expertise, along with dedicated customer support, help to make PureSpec the highest quality and most widely used verification IP solution in the industry.
PureSpec leverages a proven C-based architecture specifically designed to address modeling and verification of standard interfaces in a wide range of design and verification flows. All PureSpec products are directly integrated into all popular EDA languages and verification environments:
Languages:
- - Verilog, SystemVerilog, VHDL, Cc/C++, SystemC, 'e', OpenVERA
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Environments:
- - C/C++
- - Verilog (VCS, NC Verilog, ModelSim, etc.)
- - VHDL (NC VHDL, ModelSim, etc.)
- - Cadence Incisive, TestBuilder, Specman Elite
- - Synopsys VERA
- - CoWare N2C, ConvergenSC
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Evaluate PureSpec today!
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More about PureSpec
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