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"I am the verification lead with IBM ASIC group in Austin. We were working on an SoC which includes verifying a PCI Express core using the Denali model. We have received outstanding support from Denali Software."
"We invited Denali to drop by to give us an overview of the Denali model, which helped us make the decision to switch over from our previous mirroring scheme. That strategic move shortened the verification cycle drastically. Denali has also provided fast turn around time and extensive support of the Denali model, and thus helped us meet the project deadline. Above all, Denali exhibits superb professionalism and expertise. Thank you again for outstanding support."
Duy Huynh
Senior Engineer
IBM
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PureSpec PCI Express VIP Training
Dashcourses International PCI Express Technology and
Denali PureSpec PCI Express VIP Training
Who:Denali Customers
Where:Bay Area, CA
When:
December 10-11, 2008
Attendance is free. Register today! 
Dashcourses International and Denali have prepared a special two-day training course related to the PCI Express Base Specification. The Dashcourses International PCI Express technology course will cover the PCI-SIG's PCI Express Base Specification, including the basic architecture, the protocol stack, virtual channels, and I/O virtualization. Denali's PureSpec™ PCI Express VIP training course material will help you to improve your knowledge and skills with PureSpec PCI Express verification IP. The course covers details of all advanced features of PureSpec PCI Express verification IP and its usage.
Detailed working examples help reinforce what is discussed during the lectures and provide you with extensive tool usage experience under the guidance of Dashcourses International and Denali product specialists.
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Day 1 Course Agenda
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- The basic PCI Express architecture
- Meaning and relationship of the PCIe root complex to PCIe switches and endpoints
- PCIe configurations and enumeration
- The meaning of 'Isochronous' communications
- PCIe switching, bandwidth, and bandwidth allocation
- PureSpec PCI Express basic concepts and usage model
- Model Overview
- Active vs. Passive model
- Full stack vs. partial stack verification
- PureSpec PCI Express architecture, data flow and interfaces
- PureView and configurable features
- Configuration registers
- Simulation parameters
- PureSpec PCI Express advanced verification features
- Callbacks
- Error Injection
- Assertion coverage
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Day 2 Course Agenda
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- The PCIe Protocol Stack
- PCIe Physical Layer
- Logical and Electrical Sub-block
- Data Scrambling
- Encoding and Signaling
- PCIe Data Link Layer
- Data Link Layer services, packets, and packet construction
- Link Control and Management rules
- Data Link Layer packet rules
- Data Integrity
- PCIe Transaction Layer
- Packet and header construction
- Addressing, transaction type, and transaction usage
- Transaction Layer rules and ordering
- Power Management
- Virtual Channels
- The concept of 'virtual channels' and the PCIe term 'differentiated services'
- I/O Virtualization
- PureSpec PCI Express SR-IOV features
- SR-IOV Concepts
- Model Overview
- Model Usage
- PureSpec PCI Express Gen 3 features
- Gen 3 Concepts
- Model Overview
- Model Usage
- Debugging issues using PureSpec generated log files
- Denali Databahn PCIe Controller Overview
- Architecture of PCIe Controller
- Operation of functional blocks
- System-level performance
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Live Demo
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Throughout this course, extensive working examples will provide you with practical experience using PureSpec PCI Express Verification IP. All examples are designed to demonstrate advanced verification features of PureSpec PCI Express verification IP. Topics include:
- Creating Soma files and generating wrapper
- Configuring model using Soma file and using Denali backdoor mechanism
- Usage of Denali callback methodology
- Error injection using Denali predefined error injection capability and using callback methodology
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Audience
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- Verification Engineers who will use PureSpec PCI Express verification IP to verify their PCI Express devices
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Prerequisites
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- Basic understanding of PCI Express protocol and Verilog
Seating is limited, so register today!
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