| Denali Blueprint™ |
Blueprint automates the specification and management of control registers. From a register description language (RDL) input, Blueprint generates views for hardware and software development, verification, and documentation.
 Get Blueprint today!
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| Quote |
"SystemRDL is a robust language that addresses a critical need in SoC design today. The ability to specify control registers at a higher level of abstraction is very powerful, and integrates well with the emerging SystemVerilog methodologies for SoC design and verification."
Jonathan Michelson
Author of "The Art of Verification with System Verilog Assertions"
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About SystemRDL
The SystemRDL language was specifically designed to describe and implement a wide variety of control and status (CSR's). Using the Blueprint™ SystemRDL compiler, developers can automatically generate and synchronize register views for specification, hardware design, software development, verification, and documentation.
This solution has been proven, in numerous large SoC designs, to drastically reduce the development cycle for hardware designers, hardware verification engineers, and software developers.
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| SystemRDL Language Access |
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SystemRDL is an open language, which is made publicly available through a simple license agreement.
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| About the SystemRDL Language |
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SystemRDL is an object-oriented language with a rich set of features to enable the chip development process. There are four types of base component objects in SystemRDL:
| Base Component Objects |
| Fields |
Fields are the most basic of the base component objects. They are an abstraction of memories. Fields are used to describe wires, flip-flops, DRAM, and many other types of memories. |
| Registers |
Registers are a set of one or more fields that are accessible by software at a particular address. |
| Register Files |
A register file is a logical grouping of registers and register files. |
| Address Maps |
An address map defines the organization of the registers, register files, and address maps into a software addressable space. |
Properties can be specified for each component, which enable you to describe purpose and implementation of the component. For example, fields can be assigned access properties, such as read or write for hardware or software. The manner in which you specify the access properties determines the characteristics of the generated component design (e.g. this field is a wire, that field is a flip-flop). As another example, all components can be assigned documentation properties, such as name and description. These documentation properties are subsequently used to identify and describe components in the generated output.
In addition to the four base components, there are two specialized components:
| Specialized Component Objects |
| Signals |
Signals are similar to wires and are used to describe connectivity between other elements in the SystemRDL description. |
| Enumerations |
Represent more detailed descriptions of a set of bits and can be used for documentation and to make the code more readable. |
View a simple example using SystemRDL with Blueprint
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