Verification IP – PureSpec-USB3
PureSpec™ for USB 3.0 is the industry's most comprehensive solution for predictable verification of the compliance and compatibility of SuperSpeed USB 3.0 based designs. PureSpec for USB 3.0 enables coverage-driven verification closure and seamless integration via third-party verification planners. PureSpec features a hierarchical and configurable test plan, coverage, sequences, and constraint libraries. PureSpec verification solution includes a configurable bus functional model, protocol monitor, and complete assertion library for all components in the topology. PureSpec for USB 3.0 is architected to greatly enhance your design verification productivity, ensure high-quality, and maximum performance.
- Complete protocol validation & planning solution
- Most extensive coverage of the SuperSpeed USB 3.0 specification
- Built on PureSpec proven architecture
- Data generation and compliance suite
- Supports verification tools, languages, & methodologies
Specification Coverage
Coverage of the SuperSpeed USB 3.0 specification
PureSpec provides the most extensive coverage of the USB 3.0 specification including:
- Full timing, bus functional modeling of USB specification
- Models host, device and hub
- Full Support to all layers (framework, protocol, link, and physical)
- Power Management
- Support dual-simplex, four-wire differential signaling and 8b/10b parallel interface
- Operates in SuperSpeed, Full, or HighSpeed mode
- Detailed coverage of functional layers
- Complete USB enumeration
Fabric Topography
PureSpec for SuperSpeed USB completely models all USB 3.0 components in the topology, including the host, device and hub. A library of common USB 3.0 components configurations is available online from Denali.
| Protocol Layers | Model Highlights |
|---|---|
| Framework Layer | Completely models all of the descriptors and device states. |
| Protocol Layer | Completely models the protocol for end-to-end communication of packets for all transfer types. |
| Link Layer | Completely models LTSSM state machine, link flow control, packet framing, and link power management. |
| Physical Layer | Completely models 8b/10b and serial interfaces, scrambling/unscrambling, encoding/decoding, clock recovery, and LFPS signaling. |
Architecture
PureSpec is the industry's complete protocol validation and planning solution providing:
- Configurable test plans reduce verification efforts
- Pre-built coverage and sequence libraries
- Integration with third-party verification planners
- Compliance suite
Additional features:
- Complete assertion library with thousands of runtime checks
- Configurable BFM and protocol monitor
- Constrained random traffic generation
- Pre-defined sequence libraries
- Pre-built libraries enabling coverage-driven verification
- Monitors for interoperability testing
- Powerful error injection capability
- Cumulative functional coverage reports
Data Generation/Coverage
Constrained Random Data Generation and Coverage Driven Verification
PureSpec-USB 3.0 provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to USB 3.0 specifications. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT. In addition to interacting at the pin level, PureSpec-USB 3.0 has a procedural interface to directly load or save a memory image, read or write memory words, or trigger callbacks at different stages of data flow.
- Predefined protocol specific constraints
- PureSpec USB 3.0 supports pre-built constraints library that is compliant with the SuperSpeed USB 3.0 specification. It allows constrained random stimulus generation and ensures maximum flexibility.
- Predefined library for test sequences
- PureSpec USB 3.0 supports predefined test sequences to generate SuperSpeed USB compliant stimulus. The test sequence library allows user to create various meaningful test scenarios quickly.
- Coverage library to enable coverage-driven verification
- PureSpec USB 3.0 supports predefined coverage library which enables quick adoption to coverage-driven verification. The library contains various SuperSpeed USB specific coverage points; these help measuring functional coverage during verification process.
Language/Methodologies/Tools
Languages:- Verilog
- SystemVerilog
- VHDL
- Cc
- C++
- SystemC
- 'e'
- OpenVERA
- OVM
- VMM
- eRM
- Verilog HDL - VCS, Incisive Enterprise Simulator, ModelSim
- VHDL - ModelSim, Incisive Enterprise Simulator
- Specman Elite
- SystemC - OSCI, Incisive Enterprise Simulator
- Synopsys® VERA
- CoWare® N2C, ConvergenSC