| USB 3.0 White Paper |
|
SuperSpeed USB 3.0 Specification Revolutionizes An Established Standard
Author: Sanjiv Kumar, Director of Verification IP Products
Download Now
|
Denali's Verification IP Suite
| On-Demand Webcast |
![[IMAGE] Sean Smith](/en/images/bio/sean_smith.jpg)
Listen to Sean Smith, Director of Field Applications as he provides an overview to Denali's Verification IP suite of products. (~20min.)
View webcast now
|
|
|
PureSpec-USB 3.0
First USB 3.0 Solution to Market
PureSpec™-USB 3.0 is a complete verification IP
solution for verifying compliance and compatibility of SuperSpeed USB 3.0 designs. The PureSpec USB 3.0 product includes simulation models for host, device and hub components, and provides extensive traffic generation, protocol specific constraints and coverage libraries to greatly enhance your design verification productivity. PureSpec-USB 3.0 is architected to ensure
high-quality, high-performance, and seamless EDA integrations. A solid product platform, dedicated
customer support, and unmatched EDA modeling and verification expertise make PureSpec-USB the
best-in-class verification IP solution.
Download Now! New SuperSpeed USB 3.0 Specification whitepaper
|
| Key Features |
|
Most Extensive Coverage of the SuperSpeed USB 3.0 Specification
Fabric Topography
Built on PureSpec Proven Architecture
Data Generation and Compliance Suite
Supports Verification Languages, Methodologies and Tools
|
|
Coverage of the SuperSpeed USB 3.0 Specification |
|---|
- Full timing, bus functional modeling of USB specification
- Models host, device and hub
- Full Support to all layers (framework, protocol, link, and physical)
- Power Management
- Support dual-simplex, four-wire differential signaling and 8b/10b parallel interface
- Operates in SuperSpeed, Full or HighSpeed mode
- Detailed coverage of functional layers
- Complete USB enumeration
|
|
Fabric Topography of the USB Model
|
|---|
|
PureSpec for SuperSpeed USB completely models all USB 3.0 components in the topology, including the host, device and hub. A library of common USB 3.0 components configurations is available online from Denali.
| Protocol Layers |
Model Highlights |
| Framework Layer |
Completely models all of the descriptors and device states. |
| Protocol Layer |
Completely models the protocol for end-to-end communication of packets for all transfer types. |
| Link Layer |
Completely models LTSSM state machine, link flow control, packet framing, and link power management. |
| Physical Layer |
Completely models 8b/10b and serial interfaces, scrambling/unscrambling, encoding/decoding, clock recovery, and LFPS signaling. |
|
| Denali PureSpec Proven Architecture |
- Complete assertion library with thousands of runtime checks
- Configurable BFM and protocol monitor
- Constrained random traffic generation
- Pre-defined sequence libraries
- Pre-built libraries enabling coverage-driven verification
- Monitors for interoperability testing
- Powerful error injection capability
- Cumulative functional coverage reports
![[IMAGE] PureSpec Architecture](/en/images/products/purespec_arch_usb3.gif)
|
| Constrained Random Data Generation and Coverage Driven Verification |
|---|
|
PureSpec-USB 3.0 provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to USB 3.0 specifications. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT. In addition to interacting at the pin level, PureSpec-USB 3.0 has a procedural interface to directly load or save a memory image, read or write memory words, or trigger callbacks at different stages of data flow.
- Predefined protocol specific constraints
- PureSpec USB 3.0 supports pre-built constraints library that is compliant with the SuperSpeed USB 3.0 specification. It allows constrained random stimulus generation and ensures maximum flexibility.
- Predefined library for test sequences
- PureSpec USB 3.0 supports predefined test sequences to generate SuperSpeed USB compliant stimulus. The test sequence library allows user to create various meaningful test scenarios quickly.
- Coverage library to enable coverage-driven verification
- PureSpec USB 3.0 supports predefined coverage library which enables quick adoption to coverage-driven verification. The library contains various SuperSpeed USB specific coverage points; these help measuring functional coverage during verification process.
PureSuite provides pre-built test libraries to verify design compliance with USB 3.0 specification. PureSuite, with PureSpec USB 3.0 VIP provides a comprehensive, automated solution for functional verification of SuperSpeed USB. PureSuite, developed using SystemVerilog based methodology, exploits power of advanced verification methodology and generates stimulus to provide the most extensive coverage of the specification, apply design specific constraints and user extendable.
|
| Verification Languages, Methodologies and Tools |
|---|
- Supports all verification languages (Verilog, VHDL, C/C++, SystemC, SystemVerilog, 'e', and OpenVERA)
- Directly integrated into all advanced verification methodologies (OVM, VMM, eRM, etc.)
- Verification tool support includes:
Verilog HDL - VCS, Incisive Enterprise Simulator, ModelSim
VHDL - ModelSim, Incisive Enterprise Simulator
Specman Elite
SystemC - OSCI, Incisive Enterprise Simulator
Synopsys® VERA
CoWare® N2C, ConvergenSC
|
|
