USB 2.0 Verification IP – PureSpec
PureSpec™-USB is the industry's most comprehensive protocol validation solution for predictable verification of USB-based designs. PureSpec verification solution includes a configurable bus functional models for all host, device and hub components, protocol monitor, and complete assertion library for all components in the topology. PureSpec-USB is architected to greatly enhance your design verification productivity, ensure high-quality, and maximum performance.
- Complete protocol validation solution
- Most extensive coverage of the USB specifications
- Built on PureSpec proven architecture
- Data generation and compliance suite
- Supports verification tools, languages, & methodologies
Specification Coverage
Coverage of the USB 2.0 + OTG Specification
PureSpec-USB provides the most extensive coverage of the USB 2.0 + OTG specifications including:
- Full timing, bus functional modeling of USB 2.0 and USB OTG specifications
- Backwards compatible with USB 1.1 specifications
- Models host, device and hub
- Operates at high, full or low speed
- Supports SRP and HNP compliance checking for USB OTG
- Supports DP/DM, UTMI, UTMI+, ULPI and HSIC specifications
Fabric Topography
PureSpec-USB completely models all USB components in the topology, including the host, device and hub. A library of common USB components configurations is available online from Denali.
| Layer | Model Highlights |
|---|---|
| Protocol Layer | Completely models protocol, manages transaction requests and responses. Checks for all the transaction and packet rules. |
| Interface Layer | Completely models the physical link from the protocol layer to the simulation environment. Supports DP/ DM, UTMI, UTMI+, ULPI and HSIC interfaces. Supports reset, suspend/resume, remote wakeup. |
| Registers | Stores configuration information and model state. Supports register queries and updates through a testbench interface. |
Architecture
PureSpec is the industry's most comprehensive protocol validation solution providing:
- Complete assertion library with thousands of runtime checks
- Configurable BFM and protocol monitor
- Constrained random traffic generation
- Pre-defined sequence libraries
- Pre-built libraries enabling coverage-driven verification
- Monitors for interoperability testing
- Powerful error injection capability
- Cumulative functional coverage reports
Data Generation
PureSpec-USB provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to USB specifications. The highly integrated nature of PureSpec-USB's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT.
Language/Methodologies/Tools
Languages:- Verilog
- SystemVerilog
- VHDL
- C
- C++
- SystemC
- 'e'
- OpenVERA
- OVM
- VMM
- eRM
- Verilog HDL - VCS, Incisive Enterprise Simulator, ModelSim
- VHDL - ModelSim, Incisive Enterprise Simulator
- Specman Elite
- SystemC - OSCI, Incisive Enterprise Simulator
- Synopsys® VERA
- CoWare® N2C, ConvergenSC