| Customer Quote |
|
"Current chipsets demand higher-bandwidth support and chip-to-chip interconnectivity and Denali's IP products support the next-generation protocol requirements for design and verification of PCI Express systems. Denali's IP products help us streamline our design cycles and provide a clean roadmap for incorporating the latest specifications for our deployment of PCI Express technology."
John Sherman
Logic Design Manager
Engenio Storage Group
LSI Logic
|
| Denali Databahn™ |
|
Denali Databahn is the most trusted design IP solution for SoC interfaces such as PCI Express, DDR-SDRAM, and NAND Flash memory. Databahn controllers are fully configurable, and silicon proven in over 27 process nodes.
 Get Databahn today!
|
| Memory Report |
|
The Denali Memory Report (DMR) is now available online, in the form of weekly articles and quarterly
webcasts that address trends, analysis, and news for the semiconductor memory industry.
Access the DMR now!
|
|
|
PureSpec-USB 2.0 & OTG
PureSpec-USB is a complete verification IP solution for verifying compliance and compatibility of USB designs. PureSpec-USB includes simulation models for all host, device and hub components, and provides extensive traffic generation capabilities to greatly enhance your design verification productivity. PureSpec-USB is architected to ensure high-quality, high-performance, and seamless integrations.
Evaluate PureSpec today!
|
| Key Features |
- Full timing, bus functional modeling of USB 2.0 and USB OTG specifications
-Fully compatible with USB 1.1 specifications
- Multiple testbench and language interface
-Verilog, VHDL, C/C++, System C, e, OpenVera
- Models Host, Device and Hub
- Operates at High, Full or Low speed
- Supports DP/DM, UTMI, UTMI+ and ULPI specifications
- Supports SRP and HNP compliance checking for USB OTG
- Controllable protocol checkers
- Extensive configurability based on implementation specifics
- Monitors for interoperability testing
- Direct access to configuration, reset, power, and state registers
- User-customizable packet generation
- Pre-defined traffic libraries
- Powerful error injection capability
- Cumulative functional coverage reports
- Easy design and verification integration
|
| Fabric Topography of the USB Model |
PureSpec-USB completely models all USB components in the topology, including
the host, device and hub. A library of common USB components configurations is
available online from Denali.
| Layer |
Model Highlights |
| Protocol Layer |
Completely models protocol, manages transaction requests and responses. Checks for all the transaction and packet rules. |
| Interface Layer |
Completely models the physical link from the protocol layer to the simulation environment. Supports DP/
DM, UTMI, UTMI+ and ULPI interfaces. Supports reset, suspend/resume, remote wakeup. |
| Registers |
Stores configuration information and model state. Supports register queries and updates through a testbench interface. |
|
| Data Generation |
PureSpec-USB provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to USB specifications. The highly integrated nature of PureSpec-USB's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT.
|
| About PureSpec |
Denali's unmatched EDA modeling and verification expertise, along with dedicated customer support, help to make PureSpec the highest quality and most widely used verification IP solution in the industry.
PureSpec leverages a proven C-based architecture specifically designed to address modeling and verification of standard interfaces in a wide range of design and verification flows. All PureSpec products are directly integrated into all popular EDA languages and verification environments:
Languages:
- - Verilog, SystemVerilog, VHDL, Cc/C++, SystemC, 'e', OpenVERA
|
Environments:
- - C/C++
- - Verilog (VCS, NC Verilog, ModelSim, etc.)
- - VHDL (NC VHDL, ModelSim, etc.)
- - Cadence Incisive, TestBuilder, Specman Elite
- - Synopsys VERA
- - CoWare N2C, ConvergenSC
|
Evaluate PureSpec today!
|
More about PureSpec
|
|
Memory Blog