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SystemRDL Alliance

Use of this logo on product documentation from SystemRDL Alliance members indicates that SystemRDL was used in the development of the product, and SystemRDL descriptions may be available for that device.
Denali Databahn™

Denali Databahn is the most trusted design IP solution for SoC interfaces such as PCI Express, DDR-SDRAM, and NAND Flash memory. Databahn controllers are fully configurable, and silicon proven in over 27 process nodes.

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Memory Report

The Denali Memory Report (DMR) is now available online, in the form of weekly articles and quarterly webcasts that address trends, analysis, and news for the semiconductor memory industry.

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PureSpec SystemRDL™

PureSpec SystemRDL, now part of MMAV 2008, is verification IP (VIP) designed to automate all aspects of the verification process that relates to registers or configuration space registers (CSRs). Using PureSpec SystemRDL gives you complete control over your registers in a bus-agnostic manner, automates low-level structural testing, generate functional coverage models, and more.

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SystemRDL Resources: SystemRDL Compiler | SystemRDL Language | SystemRDL Alliance

PureSpec SystemRDL Overview

The vast numbers of on-chip registers that are part of all complex designs define the software interface to the chip, and usually represent the largest portion of the chip specification or programmer's guide. PureSpec SystemRDL eliminates the tedious and error prone process of describing registers for verification purposes while automatically providing low-level structural testing for registers. This enables design, verification, firmware and technical publications to work more efficiently from the consistent and synchronized vies of the chip design.

PureSpec SystemRDL is bus-agnostic and will work with all register interface models like PCI, AMBA, PLB, and any other user defined protocol in a variety of languages (e.g. Verilog, SystemVerilog, VHDL, Specman, Vera, and C++). Being part of the PureSpec family ensures excellent simulator support across a wealth of platforms and verification languages.

Architecture Diagram:

Key Features

Evaluate PureSpec SystemRDL 

  • Consistent API:
    PureSpec SystemRDL provides a consistent API for register accesses regardless whether you are testing at the unit, chip or system levels. This allows for easy re-use of test cases across different test benches and abstraction levels.
  • Automatic Structural Testing:
    PureSpec SystemRDL includes a robust library of traffic generation sequences designed to validate your register architecture and quickly expose any differences between the register specification and implementation.
  • Backdoor Loading and Scoring:
    When used in conjunction with Blueprints Verilog generator we can automatically backdoor loaded register values into the DUT in Zero simulation time allowing for much quicker initializations on large chip designs. This backdoor capability also provides a real time mirror of the DUT's registers for enhanced checking capabilities.
  • Functional Coverage Generation:
    When used in a language that supports functional coverage capture (Specman, Vera, SystemVerilog) PureSpec SystemRDL automates the tedious process of creating functional coverage models. These models are created in the user's native test bench language for easy integration with other aspects of the devices functional coverage model.

Simulation/Verification Tools:
  • C/C++, SystemC
  • Synopsys VCS, VERA, NTB
  • Cadence NC Verilog/VHDL, Specman Elite
  • Coware N2C, ConvergenSC
  • Novas Debussy, Verdi
  • Mentor Seamless
  • Cadence SimVision
Languages:
  • Verilog
  • SystemVerilog
  • VHDL
  • C/C++
  • SystemC
  • Specman e
  • OpenVERA

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Denali, the Denali logo, and Denali Software, Blueprint, Databahn, eMemory, MMAV, PureSpec and SystemRDL are trademarks of Denali Software, Inc. All other trademarks are of their respective owners
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