| Customer Quote |
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"Denali's reputation for verifying memory interfaces allowed us the opportunity to look at their product for PCI Express verification. As we evaluated PureSpec, we knew we had a winner when it caught a number of bugs that went undetected using other methods. We continue to be impressed by the tool's performance, and we have incorporated it into our overall verification methodology for our PCI Express interfaces."
Gopal Solanki
Vice President of Hardware Engineering
NVIDIA
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| Denali Databahn™ |
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Denali Databahn is the most trusted design IP solution for SoC interfaces such as PCI Express, DDR-SDRAM, and NAND Flash memory. Databahn controllers are fully configurable, and silicon proven in over 27 process nodes.
 Get Databahn today!
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| Memory Report |
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The Denali Memory Report (DMR) is now available online, in the form of weekly articles and quarterly
webcasts that address trends, analysis, and news for the semiconductor memory industry.
Access the DMR now!
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PureSpec-SATA
PureSpec-SATA is a complete verification IP solution for verifying compliance and compatibility of SATA designs. PureSpec-SATA includes simulation models for all protocol layers and device types, and provides extensive traffic generation capabilities to greatly enhance your design verification productivity. PureSpec-SATA is architected to ensure high-quality, high-performance, and seamless integrations.
Evaluate PureSpec today!
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| Key Features |
- Full timing, bus functional modeling of Serial ATA
-Full support of 1.0a and SATA 2.0 Extensions
- Multiple testbench and language interface
-Verilog, VHDL, C/C++, System C, e, OpenVera
- Models all SATA Components
-Host, Legacy-Master-Only, Legacy-Master-and-Slave
-Device, Port Selector, Port Multiplier
- Controllable protocol checkers and passive monitors
- Supports all protocol layers
-Physical, Link, Transport, Command, Enclosure
- Selectable pin interface
-Serial, 10-bit, PHY
- Configurability based on implementation specifics
- Direct access to configuration registers
- Detailed coverage of functional layers, including clock recovery
- User-customizable packet generation
- Pre-defined traffic libraries
- Powerful error injection capability
- Cumulative functional coverage reports
- Easy design and verification integration
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| Fabric Topography of the SATA Model |
PureSpec-SATA completely models all SATA components in the topology, including the host and one or more SATA devices. A generic model conforming to the specification can also be emulated. A library of common SATA device configurations are available online from Denali.
| Protocol Layer |
Model Highlights |
| PHY Layer |
Performs the serialization/deserialization of data; also interprets out-of-band signalling used for power
up and hot plug detection. Drives the pins at a serial or 10bit interface. |
| Link Layer |
Performs the packet framing, 8b/10b encoding/ decoding, generation and checking of CRC; also handles and checks flow control and data buffering; direct testbench interface into link layer to control and initate link layer packet traffic. |
| Transport Layer |
Interfaces to the ATA register file, interpreting commands and giving link layer blocked tasks; direct testbench interface into transport layer to control and initiate transport layer pack traffic. |
| Command Layer |
Defines sequences of Transport layer actions that are performed to execute ATA commands. |
| Enclosure Layer |
Defines a means to support industry-standard SAF_TE (SCSI Accessed Fault-Tolerant Enclosures) and SES (SCSI Enclosure Services) enclosure services. It improves the functionality of SATA storage subsystems. |
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| Data Generation |
PureSpec-SATA provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to SATA specifications. The highly integrated nature of PureSpec-SATA's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct
translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT.
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| About PureSpec |
Denali's unmatched EDA modeling and verification expertise, along with dedicated customer support, help to make PureSpec the highest quality and most widely used verification IP solution in the industry.
PureSpec leverages a proven C-based architecture specifically designed to address modeling and verification of standard interfaces in a wide range of design and verification flows. All PureSpec products are directly integrated into all popular EDA languages and verification environments:
Languages:
- - Verilog, SystemVerilog, VHDL, Cc/C++, SystemC, 'e', OpenVERA
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Environments:
- - C/C++
- - Verilog (VCS, NC Verilog, ModelSim, etc.)
- - VHDL (NC VHDL, ModelSim, etc.)
- - Cadence Incisive, TestBuilder, Specman Elite
- - Synopsys VERA
- - CoWare N2C, ConvergenSC
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Evaluate PureSpec today!
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More about PureSpec
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