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SATA Verification IP – PureSpec

PureSpec™-SATA is the industry's most comprehensive protocol validation solution for predictable verification of SATA-based designs. PureSpec verification solution includes a configurable bus functional models, protocol monitor, and complete assertion library for all components in the topology. PureSpec-SATA is architected to greatly enhance your design verification productivity, ensure high-quality, and maximum performance.

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Key Features:
  • Complete protocol validation solution
  • Most extensive coverage of the SATA specifications
  • Built on PureSpec proven architecture
  • Data generation and compliance suite
  • Supports verification tools, languages, & methodologies

Specification Coverage

Coverage of the SATA Specification

PureSpec-SATA provides the most extensive coverage of the SATA specification including:

  • Full timing, bus functional modeling of Serial ATA
    • Full support of Serial ATA 6Gb/s (Gen. 3), speed change negotiation between Gen1, Gen2, and Gen 3
    • Full support of 1.0a and SATA 2.0 Extensions
  • Multiple testbench and language interface
    • Verilog, VHDL, C/C++, System C, e, OpenVera
  • Models all SATA Components
    • Host, Legacy-Master-Only, Legacy-Master-and-Slave
    • Device, Port Selector, Port Multiplier
  • Controllable protocol checkers and passive monitors
  • Supports all protocol layers
    • Physical, Link, Transport, Command, Enclosure
  • Selectable pin interface
    • Serial, 10-bit, PHY
  • Configurability based on implementation specifics
  • Direct access to configuration registers
  • Detailed coverage of functional layers, including clock recovery
  • User-customizable packet generation
  • Pre-defined traffic libraries
  • Powerful error injection capability
  • Cumulative functional coverage reports
  • Easy design and verification integration

Fabric Topography

PureSpec-SATA completely models all SATA components in the topology, including the host and one or more SATA devices. A generic model conforming to the specification can also be emulated. A library of common SATA device configurations are available online from Denali.

LayerModel Highlights
PHY Layer Performs the serialization/deserialization of data; also interprets out-of-band signaling used for power up and hot plug detection. Drives the pins at a serial or 10bit interface.
Link Layer Performs the packet framing, 8b/10b encoding/ decoding, generation and checking of CRC; also handles and checks flow control and data buffering; direct testbench interface into link layer to control and initiate link layer packet traffic.
Transport Layer Interfaces to the ATA register file, interpreting commands and giving link layer blocked tasks; direct testbench interface into transport layer to control and initiate transport layer pack traffic.
Command LayerDefines sequences of Transport layer actions that are performed to execute ATA commands.
Enclosure LayerDefines a means to support industry-standard SAF_TE (SCSI Accessed Fault-Tolerant Enclosures) and SES (SCSI Enclosure Services) enclosure services. It improves the functionality of SATA storage subsystems.

 

Architecture

PureSpec is the industry's most comprehensive protocol validation solution providing:

  • Complete assertion library with thousands of runtime checks
  • Configurable BFM and protocol monitor
  • Constrained random traffic generation
  • Pre-defined sequence libraries
  • Pre-built libraries enabling coverage-driven verification
  • Monitors for interoperability testing
  • Powerful error injection capability
  • Cumulative functional coverage reports
PureSpec Diagram

Data Generation

PureSpec-SATA provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to SATA specifications. The highly integrated nature of PureSpec-SATA's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT.

Language/Methodologies/Tools

Languages:
  • Verilog
  • SystemVerilog
  • VHDL
  • C
  • C++
  • SystemC
  • 'e'
  • OpenVERA
Directly integrated into all advanced verification methodologies
  • OVM
  • VMM
  • eRM
Verification tool:
  • Verilog HDL - VCS, Incisive Enterprise Simulator, ModelSim
  • VHDL - ModelSim, Incisive Enterprise Simulator
  • Specman Elite
  • SystemC - OSCI, Incisive Enterprise Simulator
  • Synopsys® VERA
  • CoWare® N2C, ConvergenSC