PLB Verification IP – PureSpec
CoreConnect Buses (PLB 4/PLB6/DCR)
Under an agreement with IBM, Denali's PureSpec™ for Processor Local Bus (PLB) has been selected as the industry's primary protocol validation and planning solution for predictable verification of PLB designs. PureSpec-PLB enables coverage-driven verification closure and seamless integration via third-party verification planners. PureSpec features a hierarchical and configurable test plan, coverage, sequences and constraint libraries. PureSpec verification solution includes a configurable bus functional model, protocol monitor, and complete assertion library for all components in the topology. PureSpec-PLB is architected to greatly enhance your design verification productivity, ensure high-quality, and maximum performance.
- Complete protocol validation & planning solution
- Most extensive coverage of the PLB specification
- Built on PureSpec proven architecture
- Data generation and compliance suite
- Supports verification tools, languages, & methodologies
Coverage
Coverage of the Processor Local Bus (PLB) Specification (4.0, 6.0)
PLB is the foundation of the IBM® CoreConnect™ bus architecture for SoC designs. Additional elements of this architecture include an on chip peripheral bus (OPB), a bus bridge, and a device control register (DCR) bus. Lower performance peripherals connect to the OPB, which reduces traffic on the PLB, resulting in greater overall system performance. The DCR is used primarily for accessing status and control registers within the various PLB and OPB devices. The PLB is a high-performance bus that provides a standard interface to processor cores and other system peripherals requiring higher performance or low latency data throughput. The PLB4 version is fully synchronous, supports up to 8 masters, and is available in 32-bit, 64-bit, and 128-bit architecture versions; extendable to 256-bit. The PLB6 version is fully synchronous and supports up to 16 masters, and is available in 128-bit architecture versions and supports cache coherency.
PureSpec provides the most extensive coverage of the PLB 6.0 specification including:
- Full timing, bus functional models for PLB-4 or PLB-6 devices, supporting:
- Separate and configurable address bus, read data bus, and write data bus for each bus master
- Split/deferred completion scenarios and out-of-order data returns
- Separate read/write bus transfer qualifiers for overlapping read/write data
- Byte, half word, and word transfers (as well as unaligned half-word transfers and 3-byte transfers using byte enables)
- All masters and slaves attach to the PLB as 128-bit, 64-bit, and 32-bit devices. Slaves may support 8-bit and 16-bit bus widths if required
- All high-speed PLB features
- Assertion library linked to configurable models supporting all valid topologies
- Controllable protocol checkers, monitors for interoperability testing
- Pre-defined traffic libraries with user-customizable packet generation
- Powerful error injection/detection capability
- Cumulative functional coverage reports
- Transaction logging
Architecture
PureSpec is the industry's most comprehensive protocol validation and planning solution providing:
- Configurable test plans reduce verification efforts
- Pre-built coverage and sequence libraries
- Integration with third-party verification planners
- Compliance suite
- Complete assertion library with thousands of runtime checks
- Configurable BFM and protocol monitor
- Constrained random traffic generation
- Pre-defined sequence libraries
- Pre-built libraries enabling coverage-driven verification
- Monitors for interoperability testing
- Powerful error injection capability
- Cumulative functional coverage reports
Compliance Suite
Constrained Random Data Generation and Compliance Suite
PureSpec-PLB provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to PLB specifications. The highly integrated nature of PureSpec-PLB's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT. In addition to interacting at the pin level, PureSpec-PLB has a procedural interface to directly load or save a memory image, read or write memory words, or trigger callbacks at different stages of data flow.
Language/Methodologies/Tools
Languages:- Verilog
- SystemVerilog
- VHDL
- Cc
- C++
- SystemC
- 'e'
- OpenVERA
- OVM
- VMM
- eRM
- Verilog HDL - VCS, Incisive Enterprise Simulator, ModelSim
- VHDL - ModelSim, Incisive Enterprise Simulator
- Specman Elite
- SystemC - OSCI, Incisive Enterprise Simulator
- Synopsys® VERA
- CoWare® N2C, ConvergenSC
Customers
"We work to insure our customers have access to best-in-class products in our ecosystem, such as Denali's PureSpec, a high-quality comprehensive verification IP solution. IBM's collaboration with Denali gives designers the ability to quickly implement customized Power Architecture based applications in world-leading semiconductor technologies."
Jim Cuffney
Executive Project Manager
PowerPC Cores Development
IBM Microelectronics
"As the demand increases for interoperable and platform independent Power Architecture solutions, Denali has continually provided invaluable expertise in the toolkit development for the latest PLB specifications. IBM's collaboration with Denali gives designers the ability to quickly implement customized Power Architecture based applications in world-leading semiconductor technologies."
Michael Paczan
Chairman, Technical Committee
Power.org