PureSpec-PLB

• Full timing, bus functional models for PLB-4 or PLB-5, supporting:
  • Separate and configurable address bus, read data bus, and write data bus for each bus master
  • Split/deferred completion scenarios and out-of-order data returns
  • Separate read/write bus transfer qualifiers for overlapping read/write data
  • Byte, half word, and word transfers as well as unaligned half word transfers and 3-byte transfers using byte enables
  • All masters and slaves attach to the PLB as 128-bit, 64-bit, and 32-bit devices. Slaves may support 8-bit and 16-bit bus widths if required
  • All high-speed PLB features
• Assertion library linked to configurable models supporting all valid topologies
• Controllable protocol checkers, monitors for interoperability testing
• Pre-defined traffic libraries with user-customizable packet generation
• Powerful error injection/detection capability
• Cumulative functional coverage reports
• Transaction logging
• Easy testbench integration; efficient debugging features
• Multiple testbench and language support:
  - Verilog, SystemVerilog, VHDL, C/C++, SystemC, 'e', OpenVera

PureSpec PLB Assertion Library
The assertion library is a list of specific protocol checks the model performs based on the PLB specification. The assertion library is derived directly from the interface specification. A summary of the assertions that have been checked and not checked comprise the coverage report

PureSpec PLB Coverage Engine
Denali's built-in coverage engine provides functional coverage statistics between the tests being exercised and the PLB specification. PureSpec will automatically generate a coverage report describing the specification assertions that were or were not executed during the simulation helping ensure that the overall test plan sufficiently exercises the DUT. PureSpec also provides direct integration with coverage-based tools such as Cadence's Specman Elite. Denali can generate a coverage file that is directly readable by Specman's Coverage GUI. This allows users to easily incorporate PureSpec coverage information in with other DUT coverage information.

PureSpec Callbacks
PureSpec supports callback and call-forward for sophisticated error injection and coverage collection. For every significant event triggered in the protocol, PureSpec will trigger a callback to the testbench. These events refer to state machine transitions, packet movement and transformations, error or assertions firing, and memory or configuration register accesses. At each callback point, the test environment may call-forward and inject or manipulate packet, data, storage or state information to emulate and exercise error scenarios. Alternatively, callbacks enable the test environment to collect meaningful data about the behaviour of the DUT.

PureSpec PLB Scoreboarding
PureSpec provides built-in scoreboarding for both masters and slave devices to automatically check certain transactions. One example is on a memory reads, where PureSpec knows the memory contents and will automatically scoreboard check the data value being returned against an expected value. Instead of providing a simple bus monitor to watch for valid and invalid transactions, Denali's approach provides a device monitor that is a "reference" model of the DUT. This reference model knows all the specifics about the DUT and can watch for improper usage in addition to incorrect bus behavior, providing a much more complete device monitor.

Denali's unmatched EDA modeling and verification expertise, along with dedicated customer support, help to make PureSpec the highest quality and most widely used verification IP solution in the industry.

PureSpec leverages a proven C-based architecture specifically designed to address modeling and verification of standard interfaces in a wide range of design and verification flows. All PureSpec products are directly integrated into all popular EDA languages and verification environments: