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Denali's Verification IP Suite
On-Demand Webcast
[IMAGE] Sean Smith

Listen to Sean Smith, Director of Field Applications as he provides an overview to Denali's Verification IP suite of products. (~20min.)

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PureSpec™ Protocols

PureSpec is the industry's most trusted verification IP. PureSpec includes a configurable BFM, protocol monitor, and complete assertion library for all standard interfaces.

AMBA
CE-ATA
DFI 1,2.0,2.1
Ethernet
PLB 4/6
Serial ATA
USB 2.0 + OTG
 

PureSpec Verification IP for PCIe™
1.1, 2.0, 3.0 + IOV
Hundreds of customers
Industry de-facto standard

PureSpec for PCI Express (PCIe) is a complete verification IP (VIP) for verifying compliance and compatibility of PCIe designs. PureSpec for PCIe includes simulation models for all protocol layers and device types, and provides extensive traffic generation capabilities to greatly enhance your design verification productivity. PureSpec for PCIe is architected to ensure high-quality, high-performance and seamless integrations. Denali leads the market with PureSuite, a complementary solution, provides pre-built test cases ensuring optimal RTL bug-free quality.

Key Features

Most Extensive Coverage of the PCI Express Specification
Fabric Topography
Built on PureSpec Proven Architecture
Data Generation and Compliance Suite
Supports Verification Languages, Methodologies and Tools

Coverage of the PCIe Specification (1.1, 2.0, 3.0 and IOV)
  • Full timing, bus functional modeling of PCIe specification
  • Supports I/O Virtualization (single and multi-root)
  • Controllable rule checks matching PCI-SIG® Compliance Checklist
  • All PCIe layers and device types supported
  • PCIe power management supported
  • Direct access to configuration registers
  • Detailed coverage of functional layers
  • Complete PCIe hierarchy enumeration
  • PIPE 1.0, 2.0
Fabric Topography of the PCIe Model

PureSpec for PCIe includes models for all PCIe devices in the topology, including the root complex, swith, endpoint and PCIe-to-PCI bridge. A generic device conforming to the specification can also be emulated. Composite configurations by port, function or virtual channel are also supported. A library of common PCIe device configurations are available online from Denali

Protocol Layer Model Highlights
Transaction Layer Completely models protocol, plus manages transaction requests and completions. Checks for all the packet rules. Supports message requests as well as multi-functions.
Link Layer Completely models protocol, plus manages data integrity (CRC), supports flow control initialization.
Physical Layer Completely models protocol, plus supports power-on-state machines and training sequence, and clock recovery. 8b/10b encoding and data scrambling are modeled.
Configuration Registers Maintains configuration info in a separate memory space. Supports register queries and updates through a testbench interface.
Denali PureSpec Proven Architecture
  • Complete assertion library with thousands of runtime checks
  • Configurable BFM and protocol monitor
  • Constrained random traffic generation
  • Pre-defined sequence libraries
  • Pre-built libraries enabling coverage-driven verification
  • Monitors for interoperability testing
  • Powerful error injection capability
  • Cumulative functional coverage reports
[IMAGE] PureSpec Architecture
Constrained Random Data Generation and Compliance Suite

PureSpec for PCIe provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to PCIe specifications. The highly integrated nature of PureSpec for PCIe's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT. In addition to interacting at the pin level, PureSpec for PCIe has a procedural interface to directly load or save a memory image, read or write memory words, or trigger callbacks at different stages of data flow.

PureSuite, covers all PCIe compliance checklist items and includes thousands of configurable, directed tests. It is capable of exercising your design from both the PCIe interface and the design's application interface. Coupled with PureSpec for PCIe's assertions coverage capability, PureSuite helps to measure the compliance and interoperability of your design.
Verification Languages, Methodologies and Tools

  • Supports all verification languages (Verilog, VHDL, C/C++, SystemC, SystemVerilog, 'e', and OpenVERA)
  • Directly integrated into all advanced verification methodologies (OVM, VMM, eRM, etc.)
  • Verification tool support includes:
    Verilog HDL - VCS, Incisive Enterprise Simulator, ModelSim
    VHDL - ModelSim, Incisive Enterprise Simulator
    Specman Elite
    SystemC - OSCI, Incisive Enterprise Simulator
    Synopsys® VERA
    CoWare® N2C, ConvergenSC

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Denali, the Denali logo, and Denali Software, Blueprint, Databahn, eMemory, MMAV, PureSpec and SystemRDL are trademarks of Denali Software, Inc. All other trademarks are of their respective owners
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