PCI Express Verification IP
PCI Express 1.1, 2.0x, 3.0 + I/O Virtualization
PureSpec™-PCI Express (PCIe) is the industry's most comprehensive protocol validation and planning solution for predictable verification of PCIe-based designs. PureSpec-PCIe features a hierarchical and configurable test plan, coverage, sequences and constraint libraries. PureSpec verification solution includes a configurable bus functional model, protocol monitor, and complete assertion library for all components in the topology. PureSpec-PCIe is architected to greatly enhance your design verification productivity, ensure high-quality, and maximum performance. PureSpec-PCIe enables coverage-driven verification closure and seamless integration via third-party verification planners.
- Complete protocol validation & planning solution
- Most extensive coverage of the PCie specification
- Built on PureSpec proven architecture
- Data generation and compliance suite
- Supports verification tools, languages, & methodologies
Coverage
Coverage of the PCI Express Specification (1.1, 2.0, 3.0)
PureSpec-PCI Express provides the most extensive coverage of the PCIe specification including:
- Full timing, bus functional modeling of PCIe specification
- Supports I/O Virtualization (single and multi-root)
- Controllable rule checks matching PCI-SIG® Compliance Checklist
- All PCIe layers and device types supported
- PCIe power management supported
- Direct access to configuration registers
- Detailed coverage of functional layers
- Complete PCIe hierarchy enumeration
- PIPE 1.0, 2.0
Fabric Topography
PureSpec-PCIe includes models for all PCIe devices in the topology, including the root complex, switch, endpoint and PCIe-to-PCI bridge. A generic device conforming to the specification can also be emulated. Composite configurations by port, function or virtual channel are also supported. A library of common PCIe device configurations is available online from Denali.
| Protocol Layer | Model Highlights |
|---|---|
| Transaction Layer | Completely models protocol, plus manages transaction requests and completions. Checks for all the packet rules. Supports message requests as well as multi-functions. |
| Link Layer | Completely models protocol, plus manages data integrity (CRC), supports flow control initialization. |
| Physical Layer | Completely models protocol, plus supports power-on-state machines and training sequence, and clock recovery. 8b/10b encoding and data scrambling are modeled. |
| Configuration Registers | Maintains configuration info in a separate memory space. Supports register queries and updates through a testbench interface. |
Architecture
PureSpec is the industry's most comprehensive protocol validation and planning solution providing:
- Configurable test plans reduce verification efforts
- Pre-built coverage and sequence libraries
- Integration with third-party verification planners
- Compliance suite
- Complete assertion library with thousands of runtime checks
- Configurable BFM and protocol monitor
- Constrained random traffic generation
- Pre-defined sequence libraries
- Pre-built libraries enabling coverage-driven verification
- Monitors for interoperability testing
- Powerful error injection capability
- Cumulative functional coverage reports
Compliance Suite
Constrained Random Data Generation and Compliance Suite
PureSpec-PCIe provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to PCIe specifications. The highly integrated nature of PureSpec-PCIe's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT. In addition to interacting at the pin level, PureSpec-PCIe has a procedural interface to directly load or save a memory image, read or write memory words, or trigger callbacks at different stages of data flow.
Language/Methodologies/Tools
Languages:- Verilog
- SystemVerilog
- VHDL
- Cc
- C++
- SystemC
- 'e'
- OpenVERA
- OVM
- VMM
- eRM
- Verilog HDL - VCS, Incisive Enterprise Simulator, ModelSim
- VHDL - ModelSim, Incisive Enterprise Simulator
- Specman Elite
- SystemC - OSCI, Incisive Enterprise Simulator
- Synopsys® VERA
- CoWare® N2C, ConvergenSC
Customer Testimonials
"Denali's PureSpec verification IP is an integral component to meet PCIe Gen II specifications. Multi-core, multi-socket processor servers are unleashing computing power today that poses critical traffic needs which can be met by incorporating our latest 20Gb/s InfiniBand and 10Gb Ethernet products. Denali's world class high-quality IP solutions gave us the confidence that our devices will be PCIe Gen II compatible with best performance."
Noam Bloch
Sr. Director of Engineering
Mellanox
"Denali's PureSpec is the most trusted solution for verifying PCI Express designs. We have a veteran design team with extensive experience in the server market and they asked for Denali's PureSpec. In addition to its superior technology for exposing design issues, the widespread use of PureSpec gives us the added confidence in verifying interoperability with other PCI Express designs."
Chris Pettey
Chief Technology Officer
NextIO
"NetEffect was pleased with Denali's PureSpec PCIe VIP solutions for PCIe 1.1 and has expanded our relationship by embracing Denali's PCIe 2.0 design IP and verification IP solutions. Denali's PCIe core and PureSpec verification IP are integral enablers in meeting the PCIe Gen 2.0 specifications. Today's demanding data center networks address their increasing traffic needs by incorporating our latest accelerated 1Gb and 10Gb Ethernet products. Denali's reputation and track record speaks volumes for creating and delivering high-quality, complete IP solutions for the latest process technologies."
Terry Hulett
Vice President of Engineering
NetEffect