Ethernet Verification IP - PureSpec
PureSpec™-Ethernet is the industry's most comprehensive protocol validation solution for predictable verification of Ethernet-based designs. PureSpec verification solution includes a configurable bus functional model (for MAC and PHY component including all interfaces), protocol monitor, and complete assertion library for all components in the topology. PureSpec-Ethernet is architected to greatly enhance your design verification productivity, ensure high-quality, and maximum performance.
- Complete protocol validation solution
- Most extensive coverage of the Ethernet specifications
- Built on PureSpec proven architecture
- Data generation and compliance suite
- Supports verification tools, languages, & methodologies
Specification Coverage
Coverage of the Ethernet Specification
PureSpec-Ethernet provides the most extensive coverage of the Ethernet specification including:
- Full timing, bus functional modeling of IEEE 802-3 specifications
- Compliant with [S][X][R][G]MII, XLGMII (40G), CGMII (100G), [R]TBI, XSBI, XAUI Serial and 10bit I/F, 40GBASE-R, 100GBASE-R, backplane Ethernet (1G-KX, 10G-KX4, 10G-KR, and 40G-KR4) interface specifications
- Supports 10Mb/s, 100Mb/s, 1Gb/s, 10Gb/s, 40Gb/s, 100Gb/s
- Half Duplex (with Back Pressure) and Full Duplex Flow Control support
- Priority-based flow control operation via the priority pause and multiple queues
- Full support for CL37 1000BASE-X auto negotiation
- Full support for CL73 auto negotiation among backplane Ethernet
- Supports all frame types - Data, Pause, VLAN, Jumbo
- CRC generation and checking
- Supports MDIO interface and Station Management registers for all interfaces
- EEE support for the backplane PHY type 1G-KX, 10G-KX4 and 10G-KR with the low-power idle mode
- FEC support for 10G-KR, 40G-KR4, 40GBASE-R, and 100GBASE-R
- Controllable protocol checkers
- Extensive configurability based on implementation specifics
- Pre-defined traffic libraries
- User-customizable traffic generation
- Powerful error injection and detection capability
- Cumulative functional coverage reports
- Easy integration; efficient debugging features
Fabric Topography
PureSpec-Ethernet completely models all Ethernet components in the topology, including the MAC, PHY, media-all interfaces. A generic model conforming to the specifications can also be emulated. A library of common Ethernet component configurations is available online from Denali.
| Layer | Model Highlights |
|---|---|
| MAC Layer | Appends MAC fields to client payload on TX, strips MAC fields on RX, and performs checks. Computes CRC or uses client supplied CRC. |
| RS Layer | Converts MAC frame data into format required by the PHY side interface, adjusts data rate to the device speed, adds start and end of frame symbols (if needed), handles link fault signals from PHY. |
| PHY Layer | Completely models bit stream transmission, reception, encoding, decoding, and clock recovery & synchronization. |
| Registers | Consists of both MDIO and Denali model configuration registers. The MDIO registers can be accessed through MDIO interface or back-door API calls in the testbench. |
Architecture
PureSpec is the industry's most comprehensive protocol validation solution providing:
- Complete assertion library with thousands of runtime checks
- Configurable BFM and protocol monitor
- Constrained random traffic generation
- Pre-defined sequence libraries
- Pre-built libraries enabling coverage-driven verification
- Monitors for interoperability testing
- Powerful error injection capability
- Cumulative functional coverage reports
Data Generation
PureSpec-Ethernet provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to Ethernet specifications. The highly integrated nature of PureSpec-Ethernet's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT.
Language/Methodologies/Tools
Languages:- Verilog
- SystemVerilog
- VHDL
- C
- C++
- SystemC
- 'e'
- OpenVERA
- OVM
- VMM
- eRM
- Verilog HDL - VCS, Incisive Enterprise Simulator, ModelSim
- VHDL - ModelSim, Incisive Enterprise Simulator
- Specman Elite
- SystemC - OSCI, Incisive Enterprise Simulator
- Synopsys® VERA
- CoWare® N2C, ConvergenSC