| Customer Quote |
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"As the demand increases for interoperable and platform independent Power Architecture solutions, Denali has continually provided invaluable expertise in the toolkit development for the latest PLB specifications. IBM's collaboration with Denali gives designers the ability to quickly implement customized Power Architecture based applications in world-leading semiconductor technologies."
Michael Paczan
Chairman
Power.org Technical Committee
IBM
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| Denali Databahn™ |
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Denali Databahn is the most trusted design IP solution for SoC interfaces such as PCI Express, DDR-SDRAM, and NAND Flash memory. Databahn controllers are fully configurable, and silicon proven in over 27 process nodes.
 Get Databahn today!
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| Memory Report |
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The Denali Memory Report (DMR) is now available online, in the form of weekly articles and quarterly
webcasts that address trends, analysis, and news for the semiconductor memory industry.
Access the DMR now!
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PureSpec-Ethernet
PureSpec-Ethernet is a complete verification IP solution for verifying compliance and compatibility of Ethernet designs. PureSpec-Ethernet includes simulation models for MAC and PHY component interfaces; and provides extensive traffic generation capabilities to greatly enhance your design verification productivity. PureSpec-Ethernet is architected to ensure high-quality, high-performance, and seamless integrations.
Evaluate PureSpec today!
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| Key Features |
- Full timing, bus functional modeling of IEEE 802-3 specifications
- Multiple testbench and language interface
-Verilog, VHDL, C/C++, System C, e, OpenVera
- Compliant with [S][X][R][G]MII, [R]TBI, XSBI,
XAUI, and Serial interface specifications
- Supports 10Mb/s, 100Mb/s, 1Gb/s, 10Gb/s
- Half Duplex (with Back Pressure) and Full Duplex Flow Control support
- Full support for auto negotiation
- Supports all frame types - Data, Pause, VLAN, Jumbo
- CRC generation and checking
- Supports MDIO interface and Station Management registers for all interfaces
- Controllable protocol checkers
- Extensive configurability based on implementation specifics
- Pre-defined traffic libraries
- User-customizable traffic generation
- Powerful error injection and detection capability
- Cumulative functional coverage reports
- Easy integration; efficient debugging features
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| Fabric Topography of the Ethernet Model |
PureSpec-Ethernet completely models all Ethernet components in the topology, including the MAC, PHY, media-all interfaces. A generic model conforming to the specifications can also be emulated. A library of common Ethernet component configurations is available online from Denali.
| Layer |
Model Highlights |
| MAC Layer |
Appends MAC fields to client payload on TX, strips MAC fields on RX, and performs checks. Computes CRC or uses
client supplied CRC. |
| RS Layer |
Converts MAC frame data into format required by the PHY side interface, adjusts data rate to the device speed, adds start and end of frame symbols (if needed), handles link fault signals from PHY. |
| PHY Layer |
Completely models bit stream transmission, reception, encoding, decoding, and clock recovery & synchronization. |
| Registers |
Consists of both MDIO and Denali model configuration registers. The MDIO registers can be accessed through
MDIO interface or back-door API calls in the testbench. |
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| Data Generation |
PureSpec-Ethernet provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to Ethernet specifications. The highly integrated nature of PureSpec-Ethernet's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT.
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| About PureSpec |
Denali's unmatched EDA modeling and verification expertise, along with dedicated customer support, help to make PureSpec the highest quality and most widely used verification IP solution in the industry.
PureSpec leverages a proven C-based architecture specifically designed to address modeling and verification of standard interfaces in a wide range of design and verification flows. All PureSpec products are directly integrated into all popular EDA languages and verification environments:
Languages:
- - Verilog, SystemVerilog, VHDL, Cc/C++, SystemC, 'e', OpenVERA
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Environments:
- - C/C++
- - Verilog (VCS, NC Verilog, ModelSim, etc.)
- - VHDL (NC VHDL, ModelSim, etc.)
- - Cadence Incisive, TestBuilder, Specman Elite
- - Synopsys VERA
- - CoWare N2C, ConvergenSC
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Evaluate PureSpec today!
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More about PureSpec
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