CE-ATA Verification IP - PureSpec
PureSpec™-CE-ATA is the industry's most comprehensive protocol validation solution for predictable verification of CE-ATA-based designs. PureSpec verification solution includes a configurable bus functional model, protocol monitor, and complete assertion library for all components in the topology. PureSpec-CE-ATA is architected to greatly enhance your design verification productivity, ensure high-quality, and maximum performance.
- Complete protocol validation solution
- Most extensive coverage of the CE-ATA specification
- Built on PureSpec proven architecture
- Data generation and compliance suite
- Supports verification tools, languages, & methodologies
Specification Coverage
Specification Coverage
Coverage of the CE-ATA Specification
PureSpec-CE-ATA provides the most extensive coverage of the CE-ATA specification including:
- Full timing, bus functional modeling of CE-ATA specifications
- Multiple testbench and language interface -Verilog, VHDL, C/C++, System C, e, OpenVera, SystemVerilog
- Supports MMC State Machine- CMD0, CMD12, CMD39, CMD60, CMD61
- Supports ATA commands- IDENTIFY DEVICE, READ DMA EXT, WRITE DMA EXT, Software ATA reset
- Full support for all Status and Control Registers
- Models HD Storage
- Controllable protocol checkers
- Extensive configurability based on implementation specifics
- Powerful error injection and detection capability
- Cumulative functional coverage reports
- Easy integration; efficient debugging features
Fabric Topography
Fabric Topography
PureSpec CE-ATA completely models the CE-ATA host and device components in the topology. A generic model conforming to the specifications can also be emulated. A library of common CE-ATA component configurations is available online from Denali.
| Layer | Model Highlights |
|---|---|
| MMC Command Layer | The MMC Command state machine is responsible for CMD line and is in control of the MMC layer. |
| MMC Data Layer | The MMC Data state machine performs operations as requested by the command state machine and acts as a data movement engine. |
| ATA Layer | The ATA state machine defines the required ATA behavior. |
| Registers | Consists of both CE-ATA and Denali model configuration registers. These registers can be accessed through backdoor calls in the testbench. |
Architecture
PureSpec is the industry's most comprehensive protocol validation solution providing:
- Complete assertion library with thousands of runtime checks
- Configurable BFM and protocol monitor
- Constrained random traffic generation
- Pre-defined sequence libraries
- Pre-built libraries enabling coverage-driven verification
- Monitors for interoperability testing
- Powerful error injection capability
- Cumulative functional coverage reports
Data Generation
PureSpec CE-ATA provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to CE-ATA specifications. The highly integrated nature of PureSpec CE-ATA's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT.
Language/Methodologies/Tools
Languages:- Verilog
- SystemVerilog
- VHDL
- C
- C++
- SystemC
- 'e'
- OpenVERA
- OVM
- VMM
- eRM
- Verilog HDL - VCS, Incisive Enterprise Simulator, ModelSim
- VHDL - ModelSim, Incisive Enterprise Simulator
- Specman Elite
- SystemC - OSCI, Incisive Enterprise Simulator
- Synopsys® VERA
- CoWare® N2C, ConvergenSC