| Customer Quote |
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"As the demand increases for interoperable and platform independent Power Architecture solutions, Denali has continually provided invaluable expertise in the toolkit development for the latest PLB specifications. IBM's collaboration with Denali gives designers the ability to quickly implement customized Power Architecture based applications in world-leading semiconductor technologies."
Michael Paczan
Chairman
Power.org Technical Committee
IBM
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| Denali Databahn™ |
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Denali Databahn is the most trusted design IP solution for SoC interfaces such as PCI Express, DDR-SDRAM, and NAND Flash memory. Databahn controllers are fully configurable, and silicon proven in over 27 process nodes.
 Get Databahn today!
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| Memory Report |
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The Denali Memory Report (DMR) is now available online, in the form of weekly articles and quarterly
webcasts that address trends, analysis, and news for the semiconductor memory industry.
Access the DMR now!
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PureSpec CE-ATA
PureSpec CE-ATA is a complete verification IP solution for CE-ATA designs. PureSpec includes a configurable bus functional model (BFM), protocol monitor, and complete assertion library for all CE-ATA host and device components. PureSpec also provides extensive traffic generation capabilities to greatly enhance verification productivity, and to ensure compliance and interoperability for CE-ATA designs.
Evaluate PureSpec today!
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| Key Features |
- Full timing, bus functional modeling of CE-ATA specifications
- Multiple testbench and language interface -Verilog, VHDL, C/C++, System C, e, OpenVera, SystemVerilog
- Supports MMC State Machine- CMD0, CMD12, CMD39, CMD60, CMD61
- Supports ATA commands- IDENTIFY DEVICE, READ DMA EXT, WRITE DMA EXT, Software ATA reset
- Full support for all Status and Control Registers
- Models HD Storage
- Controllable protocol checkers
- Extensive configurability based on implementation specifics
- Powerful error injection and detection capability
- Cumulative functional coverage reports
- Easy integration; efficient debugging features
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| Fabric Topography of the CE-ATA Model |
PureSpec CE-ATA completely models the CE-ATA host and device components in the topology. A generic model conforming to the specifications can also be emulated. A library of common CE-ATA component configurations is available online from Denali.
| Layer |
Model Highlights |
| MMC Command Layer |
The MMC Command state machine is responsible for CMD line and is in control of the MMC layer. |
| MMC Data Layer |
The MMC Data state machine performs operations as requested by the command state machine and acts as a data movement engine. |
| ATA Layer |
The ATA state machine defines the required ATA behavior. |
| Registers |
Consists of both CE-ATA and Denali model configuration registers. These registers can be accessed through backdoor calls in the testbench. |
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| Data Generation |
PureSpec CE-ATA provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to CE-ATA specifications. The highly integrated nature of PureSpec CE-ATA's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT.
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| About PureSpec |
Denali's unmatched EDA modeling and verification expertise, along with dedicated customer support, help to make PureSpec the highest quality and most widely used verification IP solution in the industry.
PureSpec leverages a proven C-based architecture specifically designed to address modeling and verification of standard interfaces in a wide range of design and verification flows. All PureSpec products are directly integrated into all popular EDA languages and verification environments:
Languages:
- - Verilog, SystemVerilog, VHDL, Cc/C++, SystemC, 'e', OpenVERA
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Environments:
- - C/C++
- - Verilog (VCS, NC Verilog, ModelSim, etc.)
- - VHDL (NC VHDL, ModelSim, etc.)
- - Cadence Incisive, TestBuilder, Specman Elite
- - Synopsys VERA
- - CoWare N2C, ConvergenSC
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Evaluate PureSpec today!
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More about PureSpec
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