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AMBA Verification IP – PureSpec

AMBA (AXI, AHB, APB)

PureSpec™-AMBA is the industry's most comprehensive protocol validation solution for predictable verification of AMBA-based designs. PureSpec verification solution includes a configurable bus functional model, protocol monitor, and complete assertion library for all components in the topology. PureSpec-AMBA is architected to greatly enhance your design verification productivity, ensure high-quality, and maximum performance. (Note: PureSpec-AMBA is available as part of MMAV product)

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Key Features:
  • Complete protocol validation solution
  • Most extensive coverage of the AMBA specifications
  • Built on PureSpec proven architecture
  • Data generation and compliance suite
  • Supports verification tools, languages, & methodologies

AXI Spec. Coverage

Coverage of the AMBA Specification (AXI)

AMBA AXI support includes:

  • AXI specification modeling on three levels: pin, transfer, and transaction
  • Four main device types - Master, Slave, Interconnect, and Clock Controller
  • Model configuration with multiple ports (except for Clock Controller model). Each of the multiple port devices can be individually configured either as a master or a slave port with customizable address and data width
  • Flexible transaction timing (both on pin-level and transfer-level). Can be specified either through SOMA file or dynamically through the Denali register interface or through AXI transactions
  • Multiple interleaving transactions, Out-of-order transaction support
  • Automatic reordering transactions for memory coherency and maximizing performance
  • Exclusive and Locked access support
  • Flexible attributes of different client memory regions access - latencies, privileged, and secured access
  • Support for non-aligned addresses and automatic write strobe generation for non-aligned transactions
  • Modification of automatically generated transactions on the fly through the callback mechanism error injection)
  • Low-power interface support
  • Customizable error reporting

PureSpec-AMBA completely models all AXI components in the topology-Master, Slave and Interconnect. A library of common AXI components configurations is available online from Denali.

AXI ComponentModel Highlights
MasterCompletely models AXI Master device. Generates and drives transactions on to the bus.
SlaveCompletely models the AXI Slave device. Accepts transactions from AXI Master.
InterconnectSupports unlimited (user configurable) Master and Slave devices, multiple widths data and address bus, different client memory regions, all types of responses, write data interleaving, pipelined operations, out of order completions.

AHB Spec. Coverage

Coverage of the AMBA Specification (AHB)

AMBA AHB support includes:

  • AHB and AHB-Lite specification modeling on three levels - pin, transfer, and transaction
  • Four main device types - Master, Slave, Arbiter, and Decoder
  • Flexible transaction timing. Can be specified either through the SOMA file or dynamically through the Denali register interface or through transactions
  • ERROR, SPLIT, and RETRY transactions and two-cycle response
  • Customizable address and data width
  • Locked transaction sequence support
  • Arbitration with flexible priority-oriented algorithm
  • Flexible attributes of different client memory regions access - latencies, split-transaction parameters
  • Modification of automatically generated transactions on the fly through the callback mechanism(error injection)
  • Customizable error reporting

PureSpec-AMBA completely models all AHB components in the topology-Master, Slave, Decoder and Arbiter.

AHB ComponentModel Highlights
MasterModels AHB master component. It can be used either in Monitor or Device mode. Generates and drives AHB bus transfers from high AHB transactions in device mode.
Slave Models AHB slave component. It can be used either in Monitor or Device mode. Accepts AHB transfers from the bus and generates appropriate response in device mode.
Decoder Models AHB decoder component. It can be used either in Monitor or Device mode.
Arbiter Models AHB Arbiter component. It can be used either in Monitor or Device mode. In device mode it supports arbitration schemes with flexible priority-oriented algorithm

APB Spec. Coverage

Coverage of the AMBA Specification (APB)

AMBA APB support includes:

  • APB specification modeling on two levels - pin and transaction
  • Two device types - Master and Slave
  • Flexible transaction timing (at both the pin-level and transaction-level). Can be specified either through SOMA files or dynamically through the Denali register interface or transactions
  • Customizable address and data width
  • Support for non-aligned addresses
  • Customizable memory regions to control memory access and latency
  • Modification of automatically generated transactions on the fly through the callback mechanism (error injection)
  • Customizable error reporting.

PureSpec-AMBA completely models all APB components in the topology - Master and Slave.

APB ComponentModel Highlights
Master Models APB master component. It can be used either in Monitor or Device mode. Generates and drives APB bus transfers from high APB transactions in device mode.
Slave Models APB slave component. It can be used either in Monitor or Device mode. Accepts APB transfers from the bus and generates appropriate response in device mode.

Architecture

PureSpec is the industry's most comprehensive protocol validation solution providing:

  • Complete assertion library with thousands of runtime checks
  • Configurable BFM and protocol monitor
  • Constrained random traffic generation
  • Pre-defined sequence libraries
  • Pre-built libraries enabling coverage-driven verification
  • Monitors for interoperability testing
  • Powerful error injection capability
  • Cumulative functional coverage reports
PureSpec

Language/Methodologies/Tools

Languages:
  • Verilog
  • SystemVerilog
  • VHDL
  • C
  • C++
  • SystemC
  • 'e'
  • OpenVERA
Directly integrated into all advanced verification methodologies
  • OVM
  • VMM
  • eRM
Verification tool:
  • Verilog HDL - VCS, Incisive Enterprise Simulator, ModelSim
  • VHDL - ModelSim, Incisive Enterprise Simulator
  • Specman Elite
  • SystemC - OSCI, Incisive Enterprise Simulator
  • Synopsys® VERA
  • CoWare® N2C, ConvergenSC