| Customer Quote |
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"AMCC values working with leading IP providers, such as Denali, who can provide high-quality products to help us achieve our design requirements in the most cost-effective manner. In order to get to market quickly with lower risk of integration errors, AMCC chose Denali verification IP architected for seamless integration into our advanced SystemVerilog design and verification methodology. Denali's products' performance and integration gives us confidence that our end-products will properly interoperate with these industry standard interfaces."
Vu Nguyen
VP of Engineering
AMCC
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| Denali Databahn™ |
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Denali Databahn is the most trusted design IP solution for SoC interfaces such as PCI Express, DDR-SDRAM, and NAND Flash memory. Databahn controllers are fully configurable, and silicon proven in over 27 process nodes.
 Get Databahn today!
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| Memory Report |
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The Denali Memory Report (DMR) is now available online, in the form of weekly articles and quarterly
webcasts that address trends, analysis, and news for the semiconductor memory industry.
Access the DMR now!
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PureSpec-AMBA
PureSpec-AMBA is a complete verification IP solution for verifying AMBA based designs, including the AXI, AHB, and APB protocols. PureSpec-AMBA includes simulation models for Master, Slave and Interconnect components, and provides extensive traffic generation capabilities to greatly enhance your design verification productivity. PureSpec is architected to ensure high-quality, high-performance, and seamless integrations.
Evaluate PureSpec for your AMBA-based designs today!
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| Key Features |
- Full timing, bus functional modeling of AMBA AXI, AHB, and APB specifications
- Multiple testbench and language interface
- -Verilog, VHDL, C/C++, System C, e, OpenVera
- Models Master, Slave and Interconnect
- Supports any valid AMBA topology
- Customizable data and address widths support
- Low Power Mode support available
- Supports SASD, SAMD, MAMD
- Flexible transaction timing
- Support for pipelined operation, out-of-order completion, multiple interleaving transactions, non-aligned address, etc.
- Controllable protocol checkers
- Extensive configurability based on implementation specifics
- Monitors for interoperability testing
- User-customizable packet generation
- Pre-defined traffic libraries
- Powerful error injection capability
- Cumulative functional coverage reports
- Easy design and verification integration
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| Fabric Topography of the AXI Model |
PureSpec-AMBA completely models all AXI components in the topology- Master, Slave and Interconnect. A library of common AXI components configurations is available online from Denali.
| AXI Component |
Model Highlights |
| Master |
Completely models AXI Master device. Generates and drives transactions on to the bus. |
| Slave |
Completely models the AXI Slave device. Accepts transactions from AXI Master. |
| Interconnect |
Supports unlimited (user configurable) Master and Slave devices, multiple widths data and address bus, different client memory regions, all types of responses, write data interleaving, pipelined operations, out of order completions. |
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| About PureSpec |
Denali's unmatched EDA modeling and verification expertise, along with dedicated customer support, help to make PureSpec the highest quality and most widely used verification IP solution in the industry.
PureSpec leverages a proven C-based architecture specifically designed to address modeling and verification of standard interfaces in a wide range of design and verification flows. All PureSpec products are directly integrated into all popular EDA languages and verification environments:
Languages:
- - Verilog, SystemVerilog, VHDL, Cc/C++, SystemC, 'e', OpenVERA
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Environments:
- - C/C++
- - Verilog (VCS, NC Verilog, ModelSim, etc.)
- - VHDL (NC VHDL, ModelSim, etc.)
- - Cadence Incisive, TestBuilder, Specman Elite
- - Synopsys VERA
- - CoWare N2C, ConvergenSC
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Evaluate PureSpec today!
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More about PureSpec
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