PureSpec™

The complexity of today's interface standards makes it impractical for most ASIC teams to both design the interface to the standard, and create the modeling and verification environment to ensure compliance. PureSpec verification IP addresses this problem, and provides ASIC developers with a high-quality modeling and verification environment to ensure full compliance and optimal performance, and advanced verification methodologies, e.g., OVM, VMM, eRM, etc.

Key Features:

New! PureSpec for USB 3.0 

•   Completely models all aspects of the protocol
•   Built-in assertions library to check protocol rules
•   Shadow-reference model of DUT
•   Configurable based on Denali SOMA™ language
•   Programmable data/traffic generation
•   Cumulative functional coverage reports
•   Error injection, detection
•   Transaction history database
•   Sophisticated scoreboarding
•   Extensible callbacks
•   C-based architecture for highest performance

PureSpec leverages a proven C-based architecture specifically designed to address modeling and verification of standard interfaces in a wide range of design and verification flows. All PureSpec products are directly integrated into all popular EDA languages and verification environments:

Languages:

•   Verilog, SystemVerilog, VHDL, Cc/C++, SystemC, 'e', OpenVERA

Environments:

•   C/C++
•   Verilog (VCS, Incisive Enterprise Simulator, ModelSim, etc.)
•   VHDL (Incisive Enterprise Simulator, ModelSim, etc.)
•   Cadence Incisive Enterprise Simulator, Specman Elite
•   Synopsys VERA
•   CoWare N2C, ConvergenSC

(details, see the full list of EDA tool integrations)

In addition, to seamless testbench interfaces and consistent error reporting, PureSpec supports built-in and user-defined assertions which can provide call-backs to the testbench environment. Extensible PureSpec callbacks answer key functional coverage questions such as:

• Did I exercise all bus operations (reads, writes, etc.)?
• Did I thoroughly exercise the arbiter, master, slave devices?
• Were all data bits exercised?
• Did I hit all the possible configurations/states?
• Were there any protocol or timing violations?

PureSpec has quickly become the de-facto standard platform for protocol Verification IP. Our dedicated customer support and unmatched EDA modeling and verification expertise contribute to make PureSpec the best-in-class verification IP solution.

Find out how PureSpec can speed your product design; contact a Denali Sales representative now.