Memory Models MMAV
MMAV verification IP is the industry's standard solution for verifying memory interfaces and ensuring system correctness. MMAV dramatically enhances verification by enabling you to observe and operate on system-level data transactions during simulation. This approach is key to optimizing regressions and accelerating your overall verification process.
The new MMAV 2010 package (now available) expands the number of supported memories and protocols with CE-ATA, eMMC 4.4, I2C, LBA NAND, LL DRAM, SD 3.0, SDIO (Host) and Toggle NAND. MMAV 2010 supports a wide range of advanced verification features to aid debugging - from assertions and callbacks to catch erroneous data transactions, to logical address mapping, error injection and transaction logging.
- High-quality memory models - Vendor Certified
- Advanced verification features
- Second-sourcing options with variable memories
- Support for all commercial verification tools, languages, & methodologies
Architecture
MMAV includes comprehensive simulation models for various technologies and certified from various vendors including:
- All DRAM including DDR1, DDR2, DDR3, Mobile SDR/DDR, Mobile DDR2, GDDR2, GDDR3, GDDR4, GDDR5, etc.
- All SRAM including QDR, PSRAM, etc.
- All Flash including NOR, NAND, OneNAND, ONFi, ToggleNAND, LBA NAND, etc.
- All Media Card memories including CE-ATA, CompactFlash, SDCard, SD3.0, eSD(embedded SDCard), Memory Stick, Memory Stick Pro, MMC, eMMC 4.4, etc.
- All protocols including AMBA (AXI, APB, AHB), DFI (DDR PHY Interface), I2C, OCP, SDIO (host), etc.
Modeling/Simulation
Denali's MMAV product provides the most complete solution for modeling and simulating memory. Denali continues to provide the highest quality models for any memory device, in any verification environment in support of over 500 leading edge companies.
MMAV utilizes a powerful and effective approach to modeling memory. The generic functionality of various memory classes and architectures are captured in a set of highly optimized 'C' models. The vendor-specific features and timing for any particular memory device are defined within a SOMA (Specification of Modeling Architecture) file. Once the MMAV model objects are linked into the simulation environment, modeling any type of memory is as simple as referencing the appropriate SOMA file for that particular memory device. MMAV automatically monitors all the timing and protocol requirements specified by the memory vendor.
The MMAV model objects are integrated to all popular simulation/verification environments, and Denali maintains a comprehensive database of over 15,000 SOMA files online at eMemory.com.
Advanced Verification
MMAV offers tremendous benefits in any system-level verification environment. At a very basic level, MMAV provides direct access to memory through commands that enable you to read, write, save, preload, and compare memory contents at any time during simulation. For advanced verification, MMAV provides:
- Robust assertions
- Error configurability
- Transition callbacks
- Assertion reports
- Creation of system memory
Callbacks catch erroneous data transactions and difficult bugs associated with: un-initialized memory accesses, redundant reads, and data overwrites. The powerful assertions can trigger breakpoints to catch bad data transactions as they happen, not thousands of cycles later when/if the erroneous condition propagates data to an observable output. Transaction callback enables to perform scoreboarding and coverage analysis. View the on-demand webcast, Utilizing Callback Features in MMAV and listen to Joshua Filliater, presents several examples of using callbacks in a SystemVerilog testbench in a variety of advanced verification methodologies.
A built-in address manager makes it easy to assemble any number of discrete memory components to form a contiguous memory address space, or "system memory". Any of the memory commands or assertions can then be applied to system memory. Other application-specific data structures include linked-lists and mirrored memory arrays.
MMAV's second-sourcing option allows designers to verify design with various memories from more than one vendor. At runtime, dynamically user can change the memory parts and verify design with another memory parts.This keeps options open to source from a new memory supplier in the future, which can be impacted by features, supply availability, and costs.
Debugging
MMAV supports PureView, a powerful debugging tool that enables you to view and edit memory contents interactively, or during post-simulation analysis. PureView also provides concise memory transaction data in the form of a history window that displays the transaction history for the device, or all transactions associated with a specific memory location. PureView also accelerates waveform level debugging with popular tools enabling synchronized viewing of waveform information, memory data, and memory transactions.
Language/Tool Support
Denali verification IP is integrated with all popular EDA tools and languages, and supports all advanced verification methodologies (i.e., VMM, OVM, eRM, etc.). Our world-class support team works hard to ensure that you continually derive optimum value from your investment in Denali products.
Languages- Verilog
- SystemVerilog
- VHDL
- C/C++
- SystemC
- Specman e
- OpenVERA
- Verilog HDL - VCS, Incisive Enterprise Simulator, ModelSim
- VHDL - ModelSim, Incisive Enterprise Simulator
- Specman Elite
- C/C++
- SystemC
- Specman e
- OpenVERA
Resources
MMAV™ 2010 — NEW!
Sanjiv Kumar presents an in-depth look at the MMAV verification IP architecture and why it is the industry's standard solution for verifying memory interfaces and ensuring system correctness. Sanjiv covers how to enhance your overall verification process as well as many of the new MMAV 2010 package features, including: peek/poke, load/restore, error injection, memory and transaction callback, assertions report generation, errors configurability and more...
Utilizing Callback Features in MMAV
Joshua Filliater presents several examples of using callbacks in a SystemVerilog testbench in a variety of advanced verification methodologies.
Customer Testimonials
"Today's SoC design specifications necessitate high-quality IP and VIP and Denali's solutions and expertise unlike any other vendor. We were pleased with the unmatched performance and overall ease of integration of Denali's Databahn memory controllers into our chip design. We used Databahn controller and MMAV in our design to support our required DDR2 memory interface and TSMC's 65nm CMOS technology. During the design and verification phases, we found that Denali's IP and VIP were easy-to-use and to integrate which facilitated our very fast design cycle."
Rafy Carmon
Vice President
Precello Ltd.
"Wintegra customers are faced with challenging design specifications for today's programmable multi-protocol networking solutions and in the Service Provider access equipment market. Utilizing Denali's MMAV we were able to accelerate our time-to-market by verifying our DDR memory system quickly and deliver high-quality WinPath2 processors."
Yoram Yeivin
Vice President of Engineering
Wintegra, Inc.
"AMCC values working with leading IP providers, such as Denali, who can provide high-quality products to help us achieve our design requirements in the most cost-effective manner. In order to get to market quickly with lower risk of integration errors, AMCC chose Denali verification IP architected for seamless integration into our advanced SystemVerilog design and verification methodology. Denali's products' performance and integration gives us confidence that our end-products will properly interoperate with these industry standard interfaces."
Vu Nguyen
Vice President of Engineering
AMCC