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DDR Device Database: eMemory.com 
In cooperation with its Memory Vendor Program (MVP) partners, Denali maintains the worlds largest, most complete database of memory device information. eMemory.com provides access to over 15,000 SOMA files, including the latest DDR2, DDR3, GDDR, and mobile DRAM devices.
DDR Verification IP: MMAV 
Denali's MMAV Verification IP product is the industry's most
widely-used solution for modeling and simulating memory devices. MMAV utilizes SOMA memory device data to
enable the highest quality models, and provides direct integrations to all popular verification tools and languages.
DDR Controller IP: Databahn 
With over 260 design-wins, Databahn is the most trusted
solution for deploying DDR memory systems. Databahn IP is fully configurable and programmable for bandwidth,
latency, power, and system-level performance. Databahn is silicon proven in over 100 chips spanning 27 process nodes.
DDR Hard PHY: Databahn 
The 3rd generation patented architecture of Denali's latest PHY takes PHY design to the next level and delivers a fully hardened solution which can be quickly and easily integrated into your design. The GDSII PHY is closed for timing and Design For Manufacturability (DFM) and completely incorporates the I/O pads. The PHY features a high-resolution analog DLL to provide extra timing margin to the board.
DDR PHY Interface: www.ddr-phy.org 
Denali has teamed with industry leaders ARM, Intel, Samsung, and Synopsys to define a common interface protocol between memory controller logic and PHY interfaces, with a goal of reducing design and integration costs, while enabling performance and data throughput efficiency. The DDR PHY Interface (DFI) 2.0 specification (now available) is an open specification, available online at: www.ddr-phy.org
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