|
Gen2 Operation: The core supports PCIe 2.0, and the preliminary 3.0 specifications to enable 5.0 Gb/s/lane transfer rates. It will automatically negotiate speed and support link-retraining. The core is integrated to any Gen2 PHY via the PIPE 2.0 specifications and can be operated at 125MHz, 250MHz, or 500MHz with 32, 64 or 128-bit datapaths.
Single-Root I/O Virtualization: The Databahn-PCIe core provides full support of the latest Address Translation Service (ATS) specification, Single-Root I/O Virtualization (SR-IOV) specification, including physical and virtual function (VF) configuration spaces, VF Alternate Routing-ID, and Functional Level Reset (FLR) capabilities. This also includes full interrupt, AER, traffic and power management. SR-IOV is an optional capability that can be used with both PCIe 1.1, 2.0, and 3.0 configurations.
Dual-mode operation: Each instance of the core can be configured as an Endpoint (EP) or Root Complex (RC).
Power management: The core supports PCI Express link power states L0, L0s and L1 with only the main power. With auxiliary power, it can support L2 and L3 states.
Interrupt Support: The core supports all the three options for implementing interrupts in a PCI Express device. In the legacy mode, it communicates the assertion and de-assertion of interrupt conditions on the link using Assert and De-assert messages. In the MSI mode, the core signals interrupts by sending MSI messages upon the occurrence of interrupt conditions. In this mode, the core supports up to 32 interrupt vectors per function, with per-vector masking. Finally, in the MSI-X mode, Databahn supports up to 2048 distinct interrupt vectors per function with per-vector masking.
Credit management: The core performs all the link-layer credit management functions defined in the PCI Express specifications. All credit parameters are configurable.
Configurable flow-control updates: The core allows flow control updates from its receive side to be scheduled in a flexible manner, thus enabling the user to make tradeoffs between credit update frequency and its bandwidth overhead. Configurable registers control the scheduling of flow-control update DLLPs.
Replay buffer: Databahn incorporates fully configurable link-layer reply buffers for each link designed for low latency and area. The core can maintain replay state for a configurable number of outstanding packets.
Host Interface: The datapath on the host interface is configurable to be 32, 64, or 128-bits. It may be AXI or Host Application Layer (HAL) interface.
Host Application Layer Interface: Five distinct simple interfaces for master, memory, I/O, messaging, and interrupt transactions hides PCI Express complexity. The memory Read/Write interface is for access to memory controllers or DMA. The master Read/Write interface is to initiate requests from the Endpoint as a bus master. The I/O interface support PCIe I/O transactions. The messaging interface supports customer messaging across PCIe and the interrupt interface supports all interrupts from the user application to the Databahn PCIe core.
Multiple PCI functions: The core includes configuration space registers for up to 8 separate PCI functions (up to 256 functions with Alternate Routing-ID), which are active when the core is configured as EP.
Local management interface: The core provides a 32-bit management interface through which local software can read and write registers in the core. Software can access registers in the configuration space as well as local management registers (registers containing the configuration settings of the core, debug registers, status registers, etc.).
|
