| Denali Databahn™ |
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Denali Databahn is the most trusted design IP solution for SoC interfaces such as PCI Express, DDR-SDRAM, and NAND Flash memory. Databahn controllers are fully configurable, and silicon proven in over 27 process nodes.
 Get Databahn today!
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| Memory Report |
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The Denali Memory Report (DMR) is now available online, in the form of weekly articles and quarterly
webcasts that address trends, analysis, and news for the semiconductor memory industry.
Access the DMR now!
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SystemRDL & Blueprint™Using SystemRDL with Blueprint™ enables a correct-by-construction methodology, and provides dramatic increase in both engineering productivity, and quality of the resulting designs.
A key value of using SystemRDL with Blueprint™ is synchronization of the hardware design with its accompanying documentation, verification source code, driver development code, and software models. This automated approach streamlines much of the documentation effort and greatly improves communication of register modifications and fixes throughout the design cycle.
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| Using SystemRDL with Blueprint - a simple example |
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As an introduction to using Blueprint with SystemRDL, the following procedure demonstrates how to generate three different types of output from a single SystemRDL specification. For this example we will generate HTML, Verilog, and C++.
Step 1. Define a specification in a text file on your server.
The following code shows a very basic SystemRDL specification. SystemRDL keywords are shown in bold font.
Step 2. Compile your design in Blueprint, and specify the outputs
You can generate multiple output types as well as specify other options when you invoke Blueprint. For example, the following Blueprint command reads the specification from the file shown in Step 1, generates HTML, Verilog, and C++, and places the output into a directory named "output":
As Blueprint is generating output it will display messages similar to the following:
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