| Customer Quote |
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"The Blueprint system-level design tool significantly reduces integration time, helps ensure consistency and eases propagation of changes throughout the design and verification process. Atheros selected Denali because it provides an integral and valuable platform solution for SoC design."
Steve Padnos
Methodology Architect
Atheros
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| Memory Report |
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The Denali Memory Report (DMR) is now available online, in the form of weekly articles and quarterly
webcasts that address trends, analysis, and news for the semiconductor memory industry.
Access the DMR now!
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Blueprint™
Blueprint, now part of PureView and MMAV 2008, automates the creation and management of control registers, and all related models, design views and documentation. From SystemRDL(Register Description Language)input, Blueprint generates views for HW/SW development, verification, and documentation. Supported output formats include Verilog, C, C++, OpenVera, e, OVL, Frame, HTML, SPIRIT-compatible XML, MS-Word and more.
View SystemRDL webcast
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SystemRDL Resources:
SystemRDL Compiler | SystemRDL Language | SystemRDL Alliance | The SPIRIT Consortium
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| Blueprint Overview |
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The vast numbers of on-chip registers that are part of all complex designs define the software interface to the chip, and usually represent the largest portion of the chip specification or programmer's guide. Blueprint eliminates tedious and error-prone processes of manually managing registers, and enables design, verification and firmware teams to work more efficiently from consistent and synchronized views of the chip design.
Blueprint supports a pragmatic approach to system-level design that starts with our Blueprint Compiler and the SystemRDL Language. Blueprint allows users to capture register specifications textually using SystemRDL or IP-XACT, and then invokes Blueprint Compiler which will generate necessary outputs and views for design, verification, documentation, software development, post silicon debug and even enables early software development with SystemC™ Transaction Level Models. Blueprint ensures interoperability with other EDA tools by inputting and outputting IP-XACT and SystemRDL formats.
Architecture Diagram:
![[IMAGE] BluePrint Architecture](/en/images/products/blueprint_arch2.gif)
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| Key Features |
- Blueprint Compiler: Blueprint Compiler is the heart of Blueprint. Blueprint Compiler takes inputs created in SystemRDL and provides rich syntax and semantic checking and builds even the most complex of register maps-quickly! Blueprint Compiler also provides a rich API on which all the Blueprint Generators are based.
- Blueprint Generators: Blueprint Generators leverage the Blueprint Compiler API to provide a rich environment for creating a variety of output generators. Blueprint comes with the RDL generators as a reference.
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| Blueprint Supported Formats |
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Inputs: SystemRDL (Register Description Language) and IP-XACT XML
- Output Generators Provided:
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Documentation, Design IP, VIP, and Software
For questions about Blueprint, please contact, Denali Sales)
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