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Denali Tutorial 1A: Choosing and Designing Memory Interfaces for Mobile, Low-Power, and Portable Products

We are entering a period of change in the memory interfaces for mobile, low-power, and portable products. The PSRAM/NOR solution in previous generation cell phones has limited speed and density, LPDDR1 SDRAM memory is not increasing in speed as fast as the chips that use it, and newly-introduced LPDDR2 memory technology offers high-speed SDRAM and compatible high-speed NOR interfaces on the same bus. Meanwhile, the "execute in place" chip architecture is challenged by the "store and download" architecture used by systems with NAND Flash, new embedded storage cards, and the forthcoming Universal Flash Storage (UFS) interface.

Tutorial attendees will grasp a deeper understanding of the different memory choices that are and will be available, as well as various system design decisions for next-generation chips based on the available memory options.

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Denali Tutorial 2A: Understanding and Verifying a PCI Express Gen3 and SR-IOV Device

Many designers are eagerly anticipating the final PCI Express (PCIe) 3.0 specification, to be released from the PCI-SIG, with its improved performance features, such as a bit rate of 8 GB per second, and backward-compatibility with existing PCIe implementations. What additional benefits can be derived from the PCIe 3.0 specification? How can the number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies be analyzed in your verification environment?

Single Root-I/O Virtualization (SR-IOV) provides a standard mechanism for PCIe devices to be shared simultaneously by multiple virtual machines. SR-IOV allows a PCIe function to be partitioned into multiple virtual interfaces; each supporting a separate data space for I/O related functions within the PCIe hierarchy. As such, the design and verification of an SR-IOV device is a critical task in the next generation of virtual computing environments.

In this tutorial:

• Discover how our Denali’s PureSpec PCIe Gen3 solution and techniques can be utilized to efficiently verify Gen3 designs
• Learn about the SR-IOV mechanism and how this affects your PCIe device architecture
• Be introduced to the latest SR-IOV extensions of PureSpec for PCIe Verification IP
• View the demos that will highlight how to build a verification environment to verify SR-IOV and PCIe Gen3 devices

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Denali Tutorial 4A: Facing Flash Device Changes and High-Speed Memory Interfaces Challenges

As flash memory changes, there are many technical aspects required to balance performance, cost and integration. Both the increases in sector size and ECC requirement need to be looked at to decide what tradeoffs are necessary for your design. In this tutorial, attendees will benefit from a detailed look at the timing level as well as the gate level impact, high-speed NAND interfaces and the timing associated with achieving the best tradeoffs.

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Denali Tutorial 5A: Critical Power Analysis for DDR PHYs

DDR PHY design involves integrating analog components, such as DLLs, along with specialty I/O pads and digital standard cell logic. The complex timing issues garner the most attention when considering PHY design, but the mixed-signal aspect of the architecture requires careful power planning and detailed analysis. This session will describe how the Cadence Encounter Power System is used for power grid verification of DDR PHY IP provided by Denali Software.

Tutorial attendees will learn about setting up power grids, measuring IR drop, and inserting decoupling capacitors. Detailed power analysis will be performed along with a review of the signoff quality results. The DDR PHY under analysis was created with Cadence SoC Encounter using a Denali-developed flow to automate most of what has traditionally been considered a manual custom task.

Attendees will benefit by understanding how to engineer power grids using EPS in the context of a real mixed signal design. Automatic insertion of decoupling capacitance will be demonstrated along with its effects. Visualizing and quantifying IR drop will ensure the chip will work at the limits of the power supply. In sum, these techniques will remove uncertainty that leads to overly conservative power grids as well as demonstrate a signoff quality flow in use on real PHYs.

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Denali Tutorial 6A: SuperSpeed USB 3.0

SuperSpeed USB 3.0 is the exciting new standard for peripheral connectivity. Amongst other improvements, it brings a ten-fold increase in transfer speeds and enhanced power management, while remaining backwards compatible with USB 2.0. This brings new challenges to the design and verification of USB 3.0 components.

Tutorial attendees will benefit from the overview of:

• The salient features of USB 3.0 protocol, along with key differences from USB 2.0 standard
• Denali PureSpec for USB 3.0 verification IP, and how it aids in validating compliance to the new standard
• Denali PureSuite, a comprehensive, automated solution for functional verification of SuperSpeed USB

Registration Closed