Monday, July 21
9:30AM - 11:30AM
Denali Tutorial 1A: Choosing and Designing Memory Interfaces for Mobile, Low-Power, and Portable Products

We are entering a period of change in the memory interfaces for mobile, low-power, and portable products. The PSRAM/NOR solution in previous generation cell phones has limited speed and density, LPDDR1 SDRAM memory is not increasing in speed as fast as the chips that use it, and upcoming LPDDR2 memory technology will offer high-speed SDRAM and compatible high-speed NOR interfaces on the same bus. Meanwhile, the "execute in place" chip architecture is challenged by the "store and download" architecture used by systems with NAND Flash, new embedded storage cards, and the forthcoming Universal Flash Storage (UFS) interface.

This tutorial will help attendees understand the different memory choices that are available and coming soon, as well as make system design decisions for next-generation chips based on the available memory choices.

Registration Closed - SOLD OUT »

 

Monday, July 21
9:30AM - 11:30AM
Denali Tutorial 2A: Understanding and Verifying a PCI Express SR-IOV Device

Single Root-I/O Virtualization (SR-IOV) provides a standard mechanism for PCI Express (PCIe) devices to be shared simultaneously by multiple virtual machines. SR-IOV allows a PCIe function to be partitioned into multiple virtual interfaces; each supporting a separate data space for I/O related functions within the PCIe hierarchy. As such, the design and verification of an SR-IOV device is a critical task in the next generation of virtual computing environments. In this tutorial:

In this tutorial:

• Learn the SR-IOV mechanism and how this affects your PCIe device This tutorial will help attendees understand the different memory choices
• Get introduced to the latest SR-IOV extensions of Denali's PureSpec for PCIe Verification IP
• View a demonstration on how to build a verification environment to verify a SR-IOV device

Registration Closed - SOLD OUT »

 

Monday, July 21
9:30AM - 11:30AM
Denali Tutorial 3A: Increase Your Productivity with High Quality Memory Verification IP

Many verification engineers today face new memory technologies with their own specific nuances, challenges and features. In this session, attendees will learn how to utilize advanced features for simulating memories using Denali's MMAV 2008 verification IP. Denali's verification experts will discuss usage specifics (e.g. error injections, memory callback, creation of system memory, coverage collection, and scoreboard) as well as review how to download Soma files and generate wrappers, configure models using Soma file, and use Denali backdoor mechanism and callback methodology.

Registration Closed - SOLD OUT »

 

Monday, July 21
1:00PM - 3:00PM
Denali Tutorial 4A: The New Flash Memory Interfaces Challenge

In this tutorial, we will study the new ONFI2.0 and Toggle NAND device technologies and the related impact on the controller and firmware design, including issues relating to LUN addressing and interfacing of the design to the DLL and PHY. We will also explore their effect on the overall flash and consumer electronics market.

We also have a guest speaker (Michael Abraham from Micron) to explain how to take advantage of the multi-plane architectures in multi-channel (multiple flash controllers) applications.

Lastly, we will survey new flash-centric protocol and commands and see how they apply in new applications.

Registration Closed - SOLD OUT »

 

Monday, July 21
1:00PM - 3:00PM
Denali Tutorial 5A: Critical Power Analysis for DDR PHYs

DDR PHY design involves integrating analog components such as DLLs along with specialty I/O pads and digital standard cell logic. The complex timing issues garner the most attention when considering PHY design but the mixed-signal aspect of the architecture requires careful power planning and detailed analysis. This session will describe how Cadence VoltageStorm, Encounter's power system, is used for power grid verification of DDR PHY IP provided by Denali Software.

Participants will learn about setting up power grids, measuring IR drop, and inserting decoupling capacitors. Detailed power analysis will be performed along with a review of the signoff quality results.

The DDR PHY under analysis was created with Cadence SoC Encounter using a Denali-developed flow to automate most of what has traditionally been considered a manual custom task.

Participants will benefit by understanding how to engineer power grids using VoltageStorm in the context of a real mixed signal design. Automatic insertion of decoupling capacitance will be demonstrated along its effects. Visualizing and quantifying IR drop will ensure the chip will work at the limits of the power supply. In sum these techniques will remove uncertainty that leads to overly conservative power grids as well demonstrate a signoff quality flow in use on real IP.

Registration Closed - SOLD OUT »