Mahmud Hassan
Principal Architect
Prism Circuits, Inc.

DDR3 PHY Implementation Challenges

This presentation will present the challenges of implementing a full featured Jedec and DFI compliant DDR3 PHY. More complex signal integrity requirements, higher frequencies, tighter tolerances, and shrinking timing budgets mean that custom analog and digital design methods are required. Design techniques that address some of these implementation challenges will be presented.