Mohammad Sadeghi
Senior Product Marketing Manager
Cadence Design Systems

Power and Signal Integrity Challenges for Memory and Memory Controller Designers

As geometries shrink and clock frequencies increase at rapid pace, memory controllers and their PHYs are becoming more complicated with every new generation. Static and instantaneous dynamic IR drop across the design lower timing and SI budgets and cause silicon failure. Increased leakage could render silicon useless in handset devices. Temperature's impact on leakage, device speed and IR drop becomes more pronounced The impact of power grid noise across Analog, MS and digital designs need to be validated in the context of the full chip. And finally packaging starts to play an important factor in the overall power integrity of the chip. Designers looking into moving below 90nm nodes need to be aware of these challenges and take appropriate measure to address them early in the design cycle.