Badawi Dweik
Sr. Product Marketing
Manager
ARM, Inc.

Not All LPDDR Designs are Created Equal - Comprehensive Low Power DDR Interface IP

This presentation will detail the advantages of taking a hierarchical approach to designing a Low Power DDR Interface from architecture to transistor level, enabling optimum power conscious design. This discussion will detail: Criteria for choosing the right memory subsystem architecture to enable power saving attributes of memory devices, controllers, interfaces, and process. Understanding memory usages and mapping the low power attributes into various operating power modes. Ensuring the various IP blocks are optimized for all operating mode.