On May 31, Denali and Cadence announced a collaborative effort to deliver the industry's most advanced DDR-PHY solutions using Denali's Databahn PHY Architecture and Cadence's SoC Encounter and EncounterTiming System. Using the combination of Denali's Databahn DDR controller and PHY IP with the Encounter platform, customers can quickly and reliably achieve DDR memory-system implementations at 65-nanometers, supporting clock speeds in excess of 400MHz. This webcast provides an overview of the problems associated with DDR system design, and a technical overview of the recently announced DDR PHY methodology from Denali and Cadence.

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"Advanced Solutions for DDR Memory System Design" View Webcast Now!
Duration: 34 minutes

Marc Greenerg, Technical Marketing Manager IP Products, Denali Software, Inc.

David Desharnais, Product Marketing Group Director, Encounter Platform, Cadence

Overview:
Modern DDR memory system design and implementation is hailed as a serious challenge facing designers today. In this webcast, presented by Marc Greenberg from Denali Software, and David Desharnais from Cadence Design Systems, these challenges are outlined, followed by a detailed look at the recommended flow for advanced DDR PHY implementation from specification to final GDSII. Topics covered in this webcast include floorplanning, pad ring optimization, timing budgeting, signal integrity, design and timing closure, using leading CPF-enabled Cadence SoC Encounter and the Encounter Timing System for final timing, signal integrity with power signoff. The Encounter platform together with Denali's DDR-PHY methodology enables the industry's leading DDR PHY implementation flow. Learn how you can successfully apply this combined solution to solve the challenges of advanced DDR PHY implementation.