Memory Blog | Products & Solutions |
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| SoC Platforms |
| - PCIe + NAND |
| System Solutions |
| - NAND Flash |
| - DDR DRAM |
| - PCI Express |
| EDA and IP Products |
| - Design IP |
| - SystemRDL |
| - Verification IP |
| - Memory Models |
| - Embedded Software |
| Documentation |
| Product Docs |
Design Automation and Test in Europe (DATE) is Europe's premier event for electronic design and intellectual property (IP) solutions. Companies engaged in system-on-chip (SoC) development face significant challenges in reducing cost and time-to-market, while increasing performance and predictability.
Visit Denali at DATE (stand M51) to learn more about next-generation IP solutions for SoC deployment. Denali offers the leading design IP and verification IP products that deliver quality, reliability, and ease-of-integration that result in success for your designs.
Our expert staff is available to meet with you at DATE!
Schedule a meeting to learn more about Denali's industry-leading solutions for your SoC design and verification challenges, including comprehensive hardware/software IP solutions for PCI Express, DDR-SDRAM, NAND Flash, and more...
Additional Denali activities at DATE:
Denali Demo: SPIRIT Consortium's General Meeting
Description: Denali experts will host a hands-on demonstration of Blueprint™- SystemRDL™ Compiler and the integration with IP-XACT from The SPIRIT Consortium. SystemRDL will be used to describe complex register structures and operation, and then Blueprint will be used to automatically generate synthesizable register code, models, documentation and other specialized views for internal hardware design, verification and software development. In a modern SoC development environment, this flow offers several significant productivity benefits, and eliminates manual and error-prone processes of developing registers while maintaining consistent and accurate views across diverse teams involved in system designs.
Panel Session: "Bridging the Digital-Analog Domain for Memory System Design"
Moderator: Graham Prophet, Editor, EDN Europe
Panelists:
Badawi Dweik (ARM), Mark Gogolewski (Denali), Bryan Jones (Intel), Michael Ching (Rambus)
and Navraj Nandra (Synopsys)
Description: The memory controller logic and PHY interface represent the two primary design elements in DDR-DRAM memory systems, used in virtually all electronic system designs, ranging from cell phones and set-top boxes, to computers and network routers. These components require a uniquely different set of engineering skills, tools and methodologies, and thus, are often developed by separate engineering teams, or are acquired from different third-party design intellectual property (IP) vendors. Consequently, the lack of a standard interface between the two design elements has become the source of significant integration and verification costs by systems developers, controller vendors, and PHY providers. Seeking to bridge this gap, a number of experts in the semiconductor, IP and electronic design automation (EDA) industries have collaborated to define a common interface between the memory controller logic and PHY. The resulting DFI (DDR PHY Interface) specification is an open standard that is now being adopted to reduce cost, time-to-market, and increase the potential for reuse of the memory controller and PHY components that make up DDR memory systems. Listen to leading contributors in this effort as they will address the issues associated with bridging this key design gap, and how the industry can benefit from the development of a common interface specification.