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Career Opportunities
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| Verification Lead - PCI-Express Design IP |
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Description:
Responsible for verification of hardware design IP functionality and deliveries to customers. This position will be expected to architect and implement the next-generation PCIe verification architecture using SystemVerilog and state-of-the-art verification re-use methodologies. The candidate will create test plans and have the ability to execute portions or all of these plans for the design IP. This position is also responsible for debug and management of customer deliveries including functional and environmental issues. Development and management of simulation regression environment for design IP is also required.
Responsibilities:
- Develop next-generation verification architecture for Denali's configurable PCI-Express design IP
- Create and execute test plans for functional verification of the design IP
- Setup and manage simulation regressions environment
- Debug issues involved in the generation of customer deliverables
- Perform verification reviews with customers and internal design teams
Requirements:
- Strong prior experience with design verification using either of the following languages: SystemVerilog, Vera, E, Testbuilder/SystemC
- Knowledge of PCI-Express (including Gen2, IO Virtualization) or related protocol/s a strong plus
- Solid understanding of verification concepts from test plan to RTL signoff
- Good scripting skills using Perl and/or Python
- MSEE or equivalent with minimum 5-7 years of work experience
Please email resumes to: careers@denali.com
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