Blueprint™

The vast numbers of on-chip registers that are part of all complex designs define the software interface to the chip, and usually represent the largest portion of the chip specification or programmer's guide. Blueprint eliminates tedious and error-prone processes of manually managing registers, and enables design, verification and firmware teams to work more efficiently from consistent and synchronized views of the chip design.

Blueprint supports a pragmatic approach to system-level design that starts with our Blueprint Compiler and the SystemRDL Language. Blueprint allows users to capture register specifications textually using SystemRDL or IP-XACT, and then invokes Blueprint Compiler which will generate necessary outputs and views for design, verification, documentation, software development, post silicon debug and even enables early software development with SystemC™ Transaction Level Models. Blueprint ensures interoperability with other EDA tools by inputting and outputting IP-XACT and SystemRDL formats.

Architecture Diagram:

• Blueprint Compiler: Blueprint Compiler is the heart of Blueprint. Blueprint Compiler takes inputs created in SystemRDL and provides rich syntax and semantic checking and builds even the most complex of register maps-quickly! Blueprint Compiler also provides a rich API on which all the Blueprint Generators are based.
• Blueprint Generators: Blueprint Generators leverage the Blueprint Compiler API to provide a rich environment for creating a variety of output generators. Blueprint comes with the RDL generator for reference and a variety of pre-built generators which can be customized by the end users or entirely new generators can be easily crafted for custom applications. Below are some highlights of our most popular generators.
• RTL: Blueprint generates a complete synthesizble register slave including a CPU interface, address decoding logic and the register implementations. This code has been optimized for excellent results in synthesis and won't make your linter or design rule checkers complain.
• Documentation: Blueprint generates documentation in all popular formats. FrameMake, Word, HTML, and XML are all supported. Blueprint provides rich capabilities for end users to tweak documentation without writing code. Using generator options and powerful tools like cascading style sheets (css) Blueprint can generate documentation the way you want it.
• Verification: Blueprint supports a variety of feature for DV including automatic structural testing, back door register loading and functional coverage model generation to simplify the job of the DV engineer whether it be the block level, chip level or sytem level. These features are built on top of Denali's Industry-leading PureSpec platform and provide critical tools for all popular HVLs, HDLs, and simualtors.
• Software: Blueprint includes C, C++/SystemC generators for generating header files for Software engineers and also for creating Transaction Level Models (TLM) for architectural analysis or early software development.
• IP-XACT: Blueprint includes full support for The SPIRIT Consortium IP-XACT standard. Both as input and output of the Blueprint Compiler. This makes utilizing IP-XACT and Blueprint in a your design flow simple and straightforward.

Inputs: SystemRDL (Register Description Language) and IP-XACT XML

Output Generators Provided:

Documentation: Frame Maker (MIF), MS Word (RTF, HTML), XML
Design IP: Verilog RTL Source
VIP: SystemC, e, OpenVera, C,C++, System Verilog
Software: SystemC, C, C++, etc
Misc: IP-XACT, Various Logic and Protocol Analyzers, & More...

Find out how Blueprint can make your chip design more efficient; contact Denali Sales today.